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参数资料
| 型号： | ML9042-11DVWA |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 显示控制器 |
| 英文描述： | 17 X 100 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC233 |
| 封装： | DIE-233 |
| 文件页数： | 6/58页 |
| 文件大小： | 558K |
| 代理商： | ML9042-11DVWA |
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FEDL9042-01
OKI Semiconductor
ML9042-xx
14/58
FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS0/CSB and RS1. The DR is
selected when both RS0/CSB and RS1 are “H”. The IR is selected when RS0/CSB is “L” and RS1 is “H”. The ER
is selected when both RS0/CSB and RS1 are “L”. (When RS0/CSB is “H” and RS1 is “L”, the ML9042 is not
selected.)
The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character
generator RAM (CGRAM).
The microcontroller (CPU) can write but cannot read the instruction code.
The ER sets the display positions of the arbitrator and the address code of the arbitrator RAM (ABRAM).
The CPU can write but cannot read the display positions of the arbitrator.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the
DDRAM, ABRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked
by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the RW/SI pin.
Table 1 RW/SI pin status and register operation
RW/SI
RS0/CSB
RS1
Operation
L
H
Writing in the IR
H
L
H
Reading the Busy flag (BF) and the address counter (ADC)
L
H
Writing in the DR
H
Reading from the DR
L
Writing in the ER
H
L
Disabled (Not in a busy state, not performing the reads.
Note that the data bus goes into a high impedance state.)
L
H
L
Disabled (Not in a busy state, not performing the writes)
H
L
Disabled (Not in a busy state, not performing the reads.
Note that the data bus goes into a high impedance state.)
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9042 is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When RW/SI = “H”, RS0/CSB = “L” and RS1 = “H”, the data in the BF is output to the DB7.
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
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相关代理商/技术参数 |
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