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参数资料
| 型号： | ML9204-XXGA |
| 厂商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分类： | 显示控制器 |
| 英文描述： | 24 X 35 DOTS FLUORESCENT DSPL CTRL, PQFP128 |
| 封装： | 14 X 20 MM, 0.50 MM PITCH, PLASTIC, QFP-128 |
| 文件页数： | 8/42页 |
| 文件大小： | 317K |
| 代理商： | ML9204-XXGA |
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PEDL9204-02
OKI Semiconductor
ML9204-xx
15/41
Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the
CS pin to “Low” level enables a data transfer.
Data is 8 bits and is sequentially input into the DI/O pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input
into the
CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each
register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the
CS pin to “High” disables data transfer. Data input from the point when the CS pin changes from
“High” to “Low” is recognized in 8-bit units.
* When data is written to RAM (DCRAM, ADRAM, CGRAM, GCRAM) continuously, addresses are internally
incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
tDOFF
LSB
CS
CP
MSB
1st byte
LSB
MSB
2nd byte
Command and address data
tCSH
LSB
MSB
3rd byte
Character code data of the
next address
Character code data
When data is written
to DCRAM*
DA
B0 B1B2 B3 B4 B5 B6 B7
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