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参数资料
| 型号： | MM54240 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | Asynchronous Receiver/Transmitter Remote Controller |
| 中文描述： | 异步接收器/发射器遥控器 |
| 文件页数： | 3/10页 |
| 文件大小： | 187K |
| 代理商： | MM54240 |
Circuit Description
The MM54240 consists of four major logic blocks: Sequen-
tial Control, Shift Register, PWM Encoder and PWM Decod-
er.
Data Ports (D0–D7):
The data ports are bidirectional and
have three output levels (high, low and weak pull-up). The
weak pull-up mode is only available when the MM54240 is a
slave device. For the master circuit, the outputs are config-
ured with standard high and low states coincident with prop-
erly enabled CS and R. This permits direct interface or buff-
ered interface with the standard bus structure of a proces-
sor system. The first three data ports (D0, D1, D2) also
serve as status pins coincident with enabled CS and S.
*
For
the slave circuit, specialized input and output options are
available by selecting the C1 and C2 inputs. The data port
can still be read even if it is configured as an output port.
Address Ports (A0–A6):
The address ports are for the in-
put of address information into the MM54240. For the mas-
ter circuit, the input must be valid during the R and W com-
mand strobes. For the slave circuit, a unique hard-wired
code must be on the address ports. This code is the ad-
dress of the slave circuit for addressing purposes. No inter-
nal pull-ups are provided.
Mode:
This input is low for slave and high (or open) for
master selections. An internal pull-up resistor is provided.
Chip Select (CS):
This pin has an internal pull-up resistor to
V
DD
. In the master mode, CS is an input and has to be
pulled low before the R, W, or S strobes can be acknowl-
edged. When CS is a logic high, the data port pins are high
impedance. In the slave mode, CS is an output. It is a logic
‘‘0’’ when the circuit is expecting to receive a transmission.
CS is intended only for controlling a transceiver buffer de-
vice. During the receive mode, CS will produce a high-going
pulse when the dummy bit is received, but prior to the inter-
nal address compare. Thus, all slaves (addressed or not
*
The other data ports will output logic ‘‘0’’.
addressed) will produce this pulse when receiving a trans-
mission. The slave that is addressed will keep CS high until
it completes the transmission to the master.
Read/Control 1 (R/C1):
In the master mode, while CS is
active low, this input can be used to initiate either of the
following three operations depending upon the present
status of the circuit.
1. To initiate a read command
2. To enable output ports if transmission received is valid
3. To terminate read command if transmission received is
incorrect (if master is in state 4 awaiting data from slave,
a dummy read will set master to initialize)
In the slave mode, this input, together with W/C2, selects
the specialized output port configuration.
Write/Control 2 (W/C2):
In the master mode, while CS is
active low, this input can be used to initiate a write com-
mand. In the slave mode, this input, together with R/C1,
selects the specialized output port configuration.
Status (S):
In the master mode, while CS is active low, this
input enables circuit status information to be output at the
first three data ports. The other five data ports will be at
logic ‘‘0’’. In the slave mode, this input sets all the output
(D0–D7) latches to the logic ‘‘1’’ state. In the slave mode,
status cannot be interrogated.
OSC:
This input is for connection to a resistor-capacitor cir-
cuit for the on-chip oscillator. Frequency tolerance is speci-
fied for two voltage ranges. In a master-slave system, if no
one circuit has a frequency more than a factor of 2 different
from any other circuit, then, valid transmission is guaran-
teed. Nominal setting is 400 kHz.
Serial:
Input and output pin for serial transmission. Output
has open-drain configuration.
Data Format
1. Serially transmitted data
TL/F/10819–3
2. Pulse width modulation coding
TL/F/10819–4
A bit is equivalent to 96 clocks of the R-C oscillator frequency i.e.; when R-C frequency
e
400 kHz, 1 bit
e
240
m
s, 1 word
e
4.32 ms.
3
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相关代理商/技术参数 |
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