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参数资料
| 型号： | MM54C374J/883B |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 总线收发器 |
| 英文描述： | CMOS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 封装： | 0.300 INCH, CERAMIC, DIP-20 |
| 文件页数： | 6/11页 |
| 文件大小： | 190K |
| 代理商： | MM54C374J/883B |
AC Electrical Characteristics (Continued)
MM54C374MM74C374 TA e 25 C CL e 50 pF tr e tf e 20 ns unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tpd0 tpd1
Propagation Delay
VCC e 5V CL e 50 pF
150
300
ns
CLOCK to Output
VCC e 10V CL e 50 pF
65
130
ns
VCC e 5V CL e 150 pF
180
360
ns
VCC e 10V CL e 150 pF
80
160
ns
tSET-UP
Minimum Set-Up Time Data In
tHOLD e 0ns
to CLOCKLATCH ENABLE
VCC e 5V
70
140
ns
VCC e 10V
35
70
ns
tPWH tPWL
Minimum CLOCK Pulse Width
VCC e 5V
70
140
ns
VCC e 10V
50
100
ns
fMAX
Maximum CLOCK Frequency
VCC e 5V
35
70
MHz
VCC e 10V
5
10
MHz
t1H t0H
Propagation Delay OUTPUT
RL e 10k CL e 50 pF
DISABLE to High Impedance
VCC e 5V
105
210
ns
State (from a Logic Level)
VCC e 10V
60
120
ns
tH1 tH0
Propagation Delay OUTPUT
RL e 10k CL e 50 pF
DISABLE to Logic Level
VCC e 5V
105
210
ns
(from High Impedance State)
VCC e 10V
45
90
ns
tTHL tTLH
Transition Time
VCC e 5V CL e 50 pF
65
130
ns
VCC e 10V CL e 50 pF
35
70
ns
VCC e 5V CL e 150 pF
110
220
ns
VCC e 10V CL e 150 pF
70
140
ns
tr tf
Maximum CLOCK Rise
VCC e 5V
15
l
2000
m
s
and Fall Time
VCC e 10V
5
l
2000
m
s
CCLK
Input Capacitance
CLOCK Input (Note 2)
75
10
pF
COD
Input Capacitance
OUTPUT DISABLE
75
10
pF
Input (Note 2)
CIN
Input Capacitance
Any Other Input (Note 2)
5
75
pF
COUT
Output Capacitance
High Impedance
10
15
pF
State (Note 2)
CPD
Power Dissipation Capacitance
Per Package (Note 3)
250
pF
AC Parameters are guaranteed by DC correlated testing
Note 2
Capacitance is guaranteed by periodic testing
Note 3
CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C74C Family Characteristics Application Note
AN-90
Note 4
These are peak output current capabilities Continuous output current is rated at 12 mA max
4
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