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参数资料
| 型号： | MM54HC123A |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | Dual Retriggerable Monostable Multivibrator(双通道可再触发的单稳态多谐振荡器) |
| 中文描述： | 双Retriggerable单稳态触发器（双通道可再触发的单稳态多谐振荡器） |
| 文件页数： | 5/6页 |
| 文件大小： | 198K |
| 代理商： | MM54HC123A |
sistor, R
EXT
, toward V
CC
. When the voltage across C
EXT
equals V
REF2
, comparator C2 changes state causing the
output latch to reset (Q goes low) while at the same time
disabling comparator C2. This ends the timing cycle with the
monostable in the quiescent state, waiting for the next trig-
ger.
A valid trigger is also recognized when trigger input B goes
from GND to V
CC
(while input A is at GND and input clear is
at V
CC
k
). The ’HC123A can also be triggered when clear
goes from GND to V
CC
(while A is at GND and B is at
V
CC
o
).
It should be noted that in the quiescent state C
EXT
is fully
charged to V
CC
causing the current through resistor R
EXT
to
be zero. Both comparators are ‘‘off’’ with the total device
current due only to reverse junction leakages. An added
featureofthe’HC123Aisthattheoutputlatchissetviathein-
puttriggerwithoutregardtothecapacitorvoltage.Thus,prop-
agation delay from trigger to Q is independent of the value
of C
EXT
, R
EXT
, or the duty cycle of the input waveform.
RETRIGGER OPERATION
The ’HC123A is retriggered if a valid trigger occurs
l
fol-
lowed by another trigger
m
before the Q output has re-
turned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at the R/C
EXT
pin has begun to rise
from V
REF1
, but has not yet reached V
REF2
, will cause an
increase in output pulse width T. When a valid retrigger is
initiated
m
, the voltage at the R/C
EXT
pin will again drop to
V
REF1
before progressing along the RC charging curve
toward V
CC
. The Q output will remain high until time T, after
the last valid retrigger.
Because the trigger-control circuit flip-flop resets shortly af-
ter C
X
has discharged to the reference voltage of the lower
reference circuit, the minimum retrigger time, t
rr
is a function
of internal propagation delays and the discharge time of C
X
:
187
V
CC
b
0.7
Another removal/retrigger time occurs when a short clear
pulse is used. Upon receipt of a clear, the one shot must
charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger. This time is
dependent on the capacitor used and is approximately:
a
522
a
(0.3 V
CC
) C
X
t
rr
&
20
a
a
565
a
(0.256 V
CC
) C
X
[
V
CC
b
0.7
]
2
t
rr
e
196
a
640
V
CC
b
0.7
(V
CC
b
0.7)
2
ns
RESET OPERATION
These one shots may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to V
CC
by turning on transistor Q1
n
. When
the voltage on the capacitor reaches V
REF2
, the reset latch
will clear and then be ready to accept another pulse. If the
clear input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the Clear input, the output pulse T can
be made significantly shorter than the minimum pulse width
specification.
Typical Output Pulse Width vs.
Timing Components
TL/F/5206–7
Typical Distribution of Output
Pulse Width, Part to Part
TL/F/5206–8
Typical 1ms Pulse Width
Variation vs. Supply
TL/F/5206–9
Minimum R
EXT
vs.
Supply Voltage
TL/F/5206–10
Typical 1ms Pulse Width
Variation vs. Temperature
TL/F/5206–11
Note:
R and C are not subjected to temperature. The C is polypropylene.
5
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