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参数资料
| 型号： | MM54HC174/883 |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 锁存器 |
| 英文描述： | TTL/H/L SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 1/4页 |
| 文件大小： | 139K |
| 代理商： | MM54HC174/883 |
TLF5318
MM54HC174MM74HC174
Hex
D
Flip-Flops
with
Clear
January 1988
MM54HC174MM74HC174
Hex D Flip-Flops with Clear
General Description
These edge triggered flip-flops utilize advanced silicon-gate
CMOS technology to implement D-type flip-flops They pos-
sess high noise immunity low power and speeds compara-
ble to low power Schottky TTL circuits This device contains
6 master-slave flip-flops with a common clock and common
clear Data on the D input having the specified setup and
hold times is transferred to the Q output on the low to high
transition of the CLOCK input The CLEAR input when low
sets all outputs to a low state
Each output can drive 10 low power Schottky TTL equiva-
lent loads The MM54HC174MM74HC174 is functionally
as well as pin compatible to the 54LS17474LS174 All in-
puts are protected from damage due to static discharge by
diodes to VCC and ground
Features
Y
Typical propagation delay 16 ns
Y
Wide operating voltage range 2 – 6V
Y
Low input current 1 mA maximum
Y
Low quiescent current 80 mA (74HC Series)
Y
Output drive 10 LSTTL loads
Connection and Logic Diagrams
Dual-In-Line Package
TLF5318 – 1
Order Number MM54HC174 or MM74HC174
Truth Table
(Each Flip-Flop)
Inputs
Outputs
Clear
Clock
D
Q
LX
X
L
H
u
HH
H
u
LL
HL
X
Q
H e High level (steady state)
L e Low level (steady state)
X e Don’t Care
u e Transition from low to high level
Q0 e The level of Q before the indicated steady state
input conditions were established
TLF5318 – 2
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A
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