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参数资料
| 型号： | MM54HC573J |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 总线收发器 |
| 英文描述： | HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 封装： | J20A |
| 文件页数： | 1/6页 |
| 文件大小： | 107K |
| 代理商： | MM54HC573J |
MM74HC573
3-STATE Octal D-Type Latch
General Description
These high speed octal D-type latches utilize advanced
silicon-gate P-well CMOS technology. They possess the
high noise immunity and low power consumption of standard
CMOS integrated circuits, as well as the ability to drive 15
LS-TTL loads. Due to the large output drive capability and
the 3-STATE feature, these devices are ideally suited for in-
terfacing with bus lines in a bus organized system.
When the LATCH ENABLE(LE) input is high, the Q outputs
will follow the D inputs. When the LATCH ENABLE goes low,
data at the D inputs will be retained at the outputs until
LATCH ENABLE returns high again. When a high logic level
is applied to the OUTPUT CONTROL OC input, all outputs
go to a high impedance state, regardless of what signals are
present at the other inputs and the state of the storage ele-
ments.
The 54HC/74HC logic family is speed, function and pinout
compatible with the standard 54LS/74LS logic family. All in-
puts are protected from damage due to static discharge by
internal diode clamps to V
CC and ground.
Features
n
Typical propagation delay: 18 ns
n
Wide operating voltage range: 2 to 6 volts
n
Low input current: 1 A maximum
n
Low quiescent current: 80 A maximum (74HC Series)
n
Compatible with bus-oriented systems
n
Output drive capability: 15 LS-TTL loads
Connection Diagram
Truth Table
Output
Latch
Data
Output
Control
Enable
L
HHH
LH
L
LL
X
Q
0
HX
X
Z
H = high level, L = low level
Q0 = level of output before steady-state inputconditions were established.
Z = high impedance
X = Don’t care
Dual-In-Line Package
DS005212-1
Top View
Order Number MM54HC573 or MM74HC573
54HCT573 (J) 74HCT573 (N, WM)
April 1998
MM74HC573
3-ST
A
T
E
Octal
D-T
ype
Latch
1998 Fairchild Semiconductor Corporation
DS005212
www.fairchildsemi.com
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