参数资料
型号: MM54HC646
厂商: National Semiconductor Corporation
英文描述: Non-Inverting Octal Bus Transceiver/Registers
中文描述: 非反相八路总线收发器/寄存器
文件页数: 4/6页
文件大小: 198K
代理商: MM54HC646
AC Electrical Characteristics
MM54HC646/MM74HC646, MM54HC648/MM74HC648 (Continued)
V
CC
e
2.0
b
6.0V, C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C T
A
eb
55 to 125
§
C Units
Typ
Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation
Delay, SBA or SAB
Input to A or B Output
C
L
e
50 pF
C
L
e
150 pF 2.0V
2.0V
85
110
170
220
214
277
253
328
ns
ns
C
L
e
50 pF
C
L
e
150 pF 4.5V
4.5V
17
22
34
44
43
55
51
66
ns
ns
C
L
e
50 pF
C
L
e
150 pF 6.0V
6.0V
14
19
29
37
36
47
43
56
ns
ns
t
PZL
, t
PZL
Maximum Output Enable
Time, G Input or DIR to A or B
Output
R
L
e
1 k
X
C
L
e
50 pF
C
L
e
150 pF 2.0V
2.0V
80
120
175
225
219
281
263
338
ns
ns
C
L
e
50 pF
C
L
e
150 pF 4.5V
4.5V
23
31
35
45
44
56
53
68
ns
ns
C
L
e
50 pF
C
L
e
150 pF 6.0V
6.0V
21
27
30
38
37
48
45
57
ns
ns
t
PHZ
, t
PLZ
Maximum Output Disable
Time, G Input to A or B
Output
R
L
e
1 k
X
C
L
e
50 pF
2.0V
4.5V
6.0V
85
23
21
175
35
30
219
44
37
263
53
45
ns
ns
ns
t
THL
, t
TLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
60
12
10
75
15
13
90
18
15
ns
ns
ns
C
L
e
50 pF
t
S
Minimum Set Up Time
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
t
H
Minimum Hold Time
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
t
W
Minimum Pulse Width
of Clock
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
21
ns
ns
ns
t
r
, t
f
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
C
PD
Power Dissipation
Capacitance (Note 5)
90
pF
C
IN
Maximum Input Capacitance
5
10
10
10
pF
C
OUT
Maximum Output
Capacitance
15
20
20
20
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
, V
CC2
f
a
I
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
Note 6:
Refer to back of this section for Typical MM54/74HC AC Switching Waveforms and Test Circuits.
4
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