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参数资料
| 型号： | MM58274CJ |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | Microprocessor Compatible Real Time Clock |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 8/16页 |
| 文件大小： | 228K |
| 代理商： | MM58274CJ |
Functional Description
(Continued)
Control Register
There are three registers which control different operations
of the clock:
a) the clock setting register
b) the interrupt register
c) the control register.
The clock setting and interrupt registers both reside at ad-
dress 15, access to one or the other being controlled by the
interrupt select bit; data bit 1 of the control register.
The clock setting register programs the timekeeping of the
clock. The 12/24-hour mode select and the AM/PM indica-
tor for 12-hour mode occupy bits 0 and 1, respectively. Data
bits 2 and 3 set the leap year counter.
The interrupt register controls the operation of the interrupt
timer, selecting the required delay period and either single
or repeated interrupt.
The control register is responsible for controlling the opera-
tions of the clock and supplying status information to the
processor. It appears as two different registers; one with
write only access and one with read only access.
The write only register consists of a bank of four latches
which control the internal processes of the clock.
The read only register contains two output data latches
which will supply status information for the processor. Table
III shows the mapping of the various control latches and
status flags in the control register. The control register is
located at address 0.
The write only portion of the control register contains four
latches:
A logic 1 written into the test bit puts the device into test
mode. This allows setting of the oscillator frequency as well
as rapid testing of the device registers, if required. A more
complete description is given in the Test Mode section. For
normal operation the test bit is loaded with logic 0.
The clock start/stop bit stops the timekeeping of the clock
and resets to 0 the tenths of seconds counter. The time of
day may then be written into the various clock registers and
the clock restarted synchronously with an external time
source. Timekeeping is maintained thereafter.
A logic 1 written to the start/stop bit halts clock timing. Tim-
ing is restarted when the start/stop bit is written with a logic
0.
The interrupt select bit determines which of the two regis-
ters mapped onto address 15 will be accessed when this
address is selected.
A logic 0 in the interrupt select bit makes the clock setting
register available to the processor. A logic 1 selects the
interrupt register.
The interrupt start/stop bit controls the running of the inter-
rupt timer. It is programmed in the same way as the clock
start/stop bit; logic 1 to halt the interrupt and reset the tim-
er, logic 0 to start interrupt timing.
When no interrupt is programmed (interrupt control register
set to 0), the interrupt start/stop bit is automatically set to a
logic 1. When any new interrupt is subsequently pro-
grammed, timing will not commence until the start/stop bit
is loaded with 0.
In the single interrupt mode, interrupt timing stops when a
timeout occurs. The processor restarts timing by writing log-
ic 0 into the start/stop bit.
In repeated interrupt mode the interrupt timer continues to
count with no intervention by the processor necessary.
Interrupt timing may be stopped in either mode by writing a
logic 1 into the interrupt start/stop bit. The timer is reset and
can be restarted in the normal way, giving a full time delay
period before the next interrupt.
In general, the control register is set up such that writing 0’s
into it will start anything that is stopped, pull the clock out of
test mode and select the clock setting register onto the bus.
In other words, writing 0 will maintain normal clock operation
and restart interrupt timing, etc.
The read only portion of the control register has two status
outputs:
Since the MM58274C keeps real time, the time data
changes asynchronously with the processor and this may
occur while the processor is reading time data out of the
clock.
Some method of warning the processor when the time data
has changed must thus be included. This is provided for by
the data-changed flag located in bit 3 of the control register.
This flag is set by the clock setting pulse which also clocks
the time registers. Testing this bit can tell the processor
whether or not the time has changed. The flag is cleared by
a read of the control register but not by any write operations.
No other register read has any effect on the state of the
data-changed flag.
Data bit 0 is the interrupt flag. This flag is set whenever the
interrupt timer times out, pulling the interrupt output low. In a
polled interrupt routine the processor can test this flag to
determine if the MM58274C was the interrupting device.
This interrupt flag and the interrupt output are both cleared
by a read of the control register.
TABLE III. The Control Register Layout
Access (addr0)
DB3
DB2
DB1
DB0
Read From:
Data-Changed Flag
0
0
Interrupt Flag
Write To:
Test
Clock Start/Stop
0
e
Clock Run
1
e
Clock Stop
Interrupt Select
0
e
Clock Setting Register
1
e
Interrupt Register
Interrupt Start/Stop
0
e
Interrupt Run
1
e
Interrupt Stop
0
e
Normal
1
e
Test Mode
8
相关PDF资料 |
PDF描述 |
|---|---|
| MM58274C | Microprocessor Compatible Real Time Clock |
| MM58274CN | Microprocessor Compatible Real Time Clock |
| MM58274CV | Microprocessor Compatible Real Time Clock |
| MM58341 | High Voltage Display Driver |
| MM58341N | High Voltage Display Driver |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MM58274CJ-12 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:MICROPROCESSOR COMPATIBLE REAL TIME CLOCK |
| MM58274CMJ | 制造商: 功能描述: 制造商:undefined 功能描述: |
| MM58274CN | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Microprocessor Compatible Real Time Clock |
| MM58274CN-12 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:MICROPROCESSOR COMPATIBLE REAL TIME CLOCK |
| MM58274CV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Microprocessor Compatible Real Time Clock |
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