参数资料
型号: MM74HC163SJX
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 计数器
中文描述: HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16
封装: 5.30 MM, EIAJ TYPE2, SOP-16
文件页数: 5/9页
文件大小: 105K
代理商: MM74HC163SJX
5
www.fairchildsemi.com
MM74HC161
MM74HC163
AC Electrical Characteristics (Continued)
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC
2 f
+ I
CC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
Logic Waveforms
Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences
Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one and two (4) Inhibit
Symbol
Parameter
Conditions
VCC
TA = 25°CTA = 40 to 85°CTA = 55 to 125°C
Units
Typ
Guaranteed Limits
tS
Minimum Setup
2.0V
175
220
260
ns
Time Enable
4.5V
35
44
52
ns
to Clock
6.0V
30
37
44
ns
tH
Minimum Hold Time
2.0V
50
63
75
ns
Data from Clock
4.5V
10
13
15
ns
6.0V
9
11
13
ns
tH
Minimum Hold Time
2.0V
0
ns
Enable, Load or Clear
4.5V
0
ns
to Clock
6.0V
0
ns
tW
Minimum Pulse Width
2.0V
80
100
120
ns
Clock, Clear, or
4.5V
16
20
24
ns
Load
6.0V
14
17
20
ns
tTLH, tTHL
Maximum
2.0V
40
75
95
110
ns
Output Rise and
4.5V
8
15
19
22
ns
Fall Time
6.0V
7
13
16
19
ns
tr, tf
Maximum Input Rise
2.0V
1000
ns
and Fall Time
4.5V
500
ns
6.0V
400
ns
CPD
Powert Dissipation
(per package)
90
pF
Capacitance (Note 5)
CIN
Maximum Input Capacitance
5
10
pF
相关PDF资料
PDF描述
MM74HC161SJX
MM74HC4040J HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 12-BIT UP BINARY COUNTER, CDIP16
MM74HC595WMX
MM74HC597MX
MM74HC597SJX
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