参数资料
型号: MM74HC164N
厂商: Fairchild Semiconductor
文件页数: 4/9页
文件大小: 0K
描述: IC REGISTER PAR-OUT 8BIT 14-DIP
标准包装: 25
系列: 74HC
逻辑类型: 移位寄存器
输出类型: 标准
元件数: 1
每个元件的位元数: 8
功能: 串行至并行
电源电压: 2 V ~ 6 V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 14-DIP(0.300",7.62mm)
供应商设备封装: 14-DIP
包装: 管件
其它名称: 74HC164
1983 Fairchild Semiconductor Corporation
www.fairchildsemi.com
MM74HC164 Rev. 1.5.0
4
MM74HC164
8-Bit
Serial-in/P
arallel-out
Shift
Register
DC Electrical Characteristics(3)
Note:
3. For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V
values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V
respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at
the higher voltage and so the 6.0V values should be used.
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15pF, tr = tf = 6ns
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40°C
to 85°C
TA = –55°C
to 125°C
Units
Typ.
Guaranteed Limits
VIH
Minimum HIGH Level
Input Voltage
2.0
1.5
V
4.5
3.15
6.0
4.2
VIL
Maximum LOW Level
Input Voltage
2.0
0.5
V
4.5
1.35
6.0
1.8
VOH
Minimum HIGH Level
Output Voltage
2.0
VIN = VIH or VIL,
|IOUT| ≤ 20A
2.0
1.9
V
4.5
4.4
6.0
5.9
4.5
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
4.2
3.98
3.84
3.7
6.0
VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
5.7
5.48
5.34
5.2
VOL
Maximum LOW Level
Output Voltage
2.0
VIN = VIH or VIL,
|IOUT| ≤ 20A
0
0.1
V
4.5
0
0.1
6.0
0
0.1
4.5
VIN = VIH or VIL,
|IOUT| ≤ 4.0mA
0.2
0.26
0.33
0.4
6.0
VIN = VIH or VIL,
|IOUT| ≤ 5.2mA
0.2
0.26
0.33
0.4
IIN
Maximum Input
Current
6.0
VIN = VCC or GND
±0.1
±1.0
A
ICC
Maximum Quiescent
Supply Current
6.0
VIN = VCC or GND,
IOUT = 0A
8.0
80
160
A
Symbol
Parameter
Conditions
Typ.
Guaranteed
Limit
Units
fMAX
Maximum Operating Frequency
30
MHz
tPHL, tPLH
Maximum Propagation Delay, Clock to
Output
19
30
ns
tPHL
Maximum Propagation Delay, Clear to
Output
23
35
ns
tREM
Minimum Removal Time, Clear to Clock
–2
0
ns
tS
Minimum Setup Time, Data to Clock
12
20
ns
tH
Minimum Hold Time, Clock to Data
1
5
ns
tW
Minimum Pulse Width, Clear or Clock
10
16
ns
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