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参数资料
| 型号： | MM74HC643N |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 通用总线功能 |
| 英文描述： | Inverting Octal TRI-STATE Transceiver |
| 中文描述： | HC/UH SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP20 |
| 封装： | PLASTIC, DIP-20 |
| 文件页数： | 2/6页 |
| 文件大小： | 145K |
| 代理商： | MM74HC643N |
Absolute Maximum Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage DIR and G pins (V
IN
)
DC Output Voltage (V
IN
, V
OUT
)
Clamp Diode Current (I
CD
)
DC Output Current, per pin (I
OUT
)
DC V
CC
or GND Current, per pin (I
CC
)
Storage Temperature Range (T
STG
)
Power Dissipation (P
D
)
(Note 3)
S.O. Package only
b
0.5 to
a
7.0V
b
1.5 to V
CC
a
1.5V
b
0.5 to V
CC
a
0.5V
g
20 mA
g
35 mA
g
70 mA
b
65
§
C to
a
150
§
C
600 mW
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260
§
C
Operating Conditions
Min
2
Max
6
Units
V
Supply Voltage (V
CC
)
DC Input or Output Voltage
(V
IN
, V
OUT
)
Operating Temp. Range (T
A
)
MM74HC
MM54HC
0
V
CC
V
b
40
b
55
a
85
a
125
§
C
§
C
Input Rise/Fall Times
(t
r
, t
f
)
V
CC
e
2.0V
V
CC
e
4.5V
V
CC
e
6.0V
1000
500
400
ns
ns
ns
DC Electrical Characteristics
(Note 4)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
T
A
eb
55 to 125
§
C
Units
Typ
Guaranteed Limits
V
IH
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
IL
Maximum Low Level Input
Voltage
**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
V
OH
Minimum High Level Output
Voltage
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
20
m
A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
6.0 mA
l
I
OUT
l
s
7.8 mA
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
20
m
A
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
V
OL
Maximum Low Level Output
Voltage
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
V
IN
e
V
IH
or V
IL
l
I
OUT
l
s
6.0 mA
l
I
OUT
l
s
7.8 mA
V
IN
e
V
CC
or GND
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
I
IN
Input Leakage
Current (G and DIR)
6.0V
g
0.1
g
1.0
g
1.0
m
A
I
OZ
Maximum TRI-STATE Output
Leakage Current
V
OUT
e
V
CC
or GND
Enable G
e
V
IH
6.0V
g
0.5
g
5.0
g
10
m
A
I
CC
Maximum Quiescent Supply
Current
V
IN
e
V
CC
or GND
I
OUT
e
0
m
A
6.0V
8.0
80
160
m
A
Note 1:
Maximum Ratings are those values beyond which damage to the device may occur.
Note 2:
Unless otherwise specified all voltages are referenced to ground.
Note 3:
Power Dissipation temperature derating D plastic ‘‘N’’ package:
b
12 mW/
§
C from 65
§
C to 85
§
C; ceramic ‘‘J’’ package:
b
12 mW/
§
C from 100
§
C to 125
§
C.
Note 4:
For a power supply of 5V
g
10% the worst case output voltages (V
OH
, and V
OL
) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case V
IH
and V
IL
occur at V
CC
e
5.5V and 4.5V respectively. (The V
IH
value at 5.5V is 3.85V.) The worst case leakage current (I
IN
, I
CC
, and
I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**
V
IL
limits are currently tested at 20% of V
CC
. The above V
IL
specification (30% of V
CC
) will be implemented no later than Q1, CY’89.
2
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