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参数资料
| 型号： | MM74HC75J |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 通用总线功能 |
| 英文描述： | 4-Bit Bistable Latch with Q and Q Output |
| 中文描述： | HC/UH SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16 |
| 封装： | DIP-16 |
| 文件页数： | 3/4页 |
| 文件大小： | 150K |
| 代理商： | MM74HC75J |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
23
Units
t
PHL
, t
PLH
Maximum Propagation
Delay, Data to Q
Maximum Propagation
Delay, Data to Q
Maximum Propagation
Delay, Enable to Q
Maximum Propagation
Delay, Enable to Q
Minimum Set Up Time
Minimum Hold Time
Minimum Pulse Width
14
ns
t
PHL
, t
PLH
10
20
ns
t
PHL
, t
PLH
16
27
ns
t
PHL
, t
PLH
11
23
ns
t
s
t
H
t
W
20
0
16
ns
ns
ns
b
2
AC Electrical Characteristics
C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
Guaranteed Limits
T
A
eb
55 to 125
§
C
Units
Typ
t
PHL
, t
PLH
Maximum Propagation
Delay, Data to Q
2.0V
4.5V
6.0V
37
15
14
125
25
24
156
32
27
188
38
32
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay, Data to Q
2.0V
4.5V
6.0V
29
12
11
110
22
19
138
28
24
165
33
29
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay, Enable to Q
2.0V
4.5V
6.0V
40
18
16
145
29
25
181
36
31
218
44
38
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay, Enable to Q
2.0V
4.5V
6.0V
36
15
14
125
25
22
156
31
28
188
38
33
ns
ns
ns
t
s
Minimum Set Up Time
Data to Enable
2.0V
4.5V
6.0V
40
10
9
100
20
17
125
25
21
150
30
25
ns
ns
ns
t
H
Minimum Hold Time
Enable to Data
2.0V
4.5V
6.0V
b
10
b
2
b
2
0
0
0
0
0
0
0
0
0
ns
ns
ns
t
W
Minimum Enable Pulse Width
2.0V
4.5V
6.0V
40
11
9
80
16
14
100
20
18
120
24
21
ns
ns
ns
t
TLH
, t
THL
Maximum Output
Rise and Fall Time
2.0V
4.5V
6.0V
25
7
6
75
15
13
95
19
16
110
22
19
ns
ns
ns
C
PD
Power Dissipation
Capacitance (Note 5)
(per commonly
clocked latched
pair)
40
pF
C
IN
Maximum Input
Capacitance
5
10
10
10
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
3
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