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参数资料
| 型号： | MM74HC943N |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 调制器/解调器 |
| 英文描述： | Low-Voltage Adjustable Precision Shunt Regulator 3-SOT-89 -40 to 85 |
| 中文描述： | 0.3 kbps DATA, MODEM, PDIP20 |
| 封装： | DIP-20 |
| 文件页数： | 5/8页 |
| 文件大小： | 153K |
| 代理商： | MM74HC943N |
Functional Description
(Continued)
THE DEMODULATOR SECTION
The Receive Filter
The demodulator recovers the data from the received sig-
nals. The signal from the hybrid is a mixture of transmitted
signal, received signals and noise. The first stage of the
receive filter is an anti-alias filter which attenuates high fre-
quency noise before sampling occurs. The signal then goes
to the second stage of the receive filter where the transmit-
ted tones and other noise are filtered from the received sig-
nal. This is a switch capacitor nine pole filter providing at
least 60 dB of transmitted tone rejection. This also provides
high attenuation at 60Hz, a common noise component.
The Discriminator
The first stage of the discriminator is a hard limiter. The hard
limiter removes from the received signal any amplitude
modulation which may bias the demodulator toward a mark
or a space. It compares the output of the receive filter to the
voltage on the 0.1
m
F capacitor on the FTLC pin.
The hard limiter output connects to two parallel bandpass
filters in the discriminator. One filter is tuned to the mark
frequency and the other to the space frequency. The out-
puts of these filters are rectified, filtered and compared. If
the output of the mark path exceeds the output of the space
path the RXD output goes high. The opposite case sends
RXD low.
The demodulator is implemented using precision switched
capacitor techniques The highly critical comparators in the
limiter and discriminator are auto-zeroed for low offset.
Carrier Detector
The output of the discriminator is meaningful only if there is
sufficient carrier being received. This is established in the
carrier detection circuit which measures the signal on the
line. If this exceeds a certain level for a preset period (ad-
justable by the CDT pin) the CD output goes low indicating
that carrier is present. Then the carrier detect threshold is
lowered by 3 dB. This provides hysteresis ensuring the CD
output remains stable. If carrier is lost CD goes high after
the preset delay and the threshold is increased by 3 dB.
MODULATOR SECTION
The modulator consists of a frequency synthesizer and a
sine wave synthesizer. The frequency synthesizer produces
one of four tones depending on the O/A and TXD pins. The
frequencies are synthesized to high precision using a crystal
oscillator and variable dual modulus counter.
Thecountersusedrespondquicklytodatachanges,introduc-
ing negligible bit jitter while maintaining phase coherence.
The sine wave synthesizer uses switched capacitors to
‘‘look up’’ the voltages of the sine wave. This sampled sig-
nal is then further processed by switched capacitor and
continuous filters to ensure the high spectral purity required
by FCC regulations.
Applications Information
TRANSMIT LEVEL ADJUSTMENT
The transmitted power levels of Table II refer to the power
delivered to a 600
X
load from the external 600
X
source
impedance. The voltage on the load is half the TXA voltage.
This should be kept in mind when designing interface cir-
cuits which do not match the load and source inpedances.
The transmit level is programmable by placing a resistor
from TLA to V
CC
. With a 5.5k resistor the line driver trans-
mits a maximum of
b
9 dBm. Since most lines from a phone
installation to the exchange provide 3 dB of attenuation the
maximum level reaching the exchange will be
b
12 dBm.
This is the maximum level permitted by most telephone
companies. Thus with this programming the MM74HC943
will interface to most telephones. This arrangement is called
the ‘‘permissive arrangement.’’ The disadvantage with the
permissive arrangement is that when the loss from a phone
to the exchange exceeds 3 dB, no compensation is made
and SNR may be unnecessarily degraded.
TABLE II. Universal Service Order Code Resistor Values
Line
Loss
(dB)
Transmit
Level
(dBm)
Programming
Resistor (R
TLA
)
(
X
)
0
1
2
3
b
12
b
11
b
10
b
9
Open
19,800
9,200
5,490
CARRIER DETECT THRESHOLD ADJUSTMENT
The carrier detect threshold is directly proportional to the
voltage on CDA. This pin is connected internally to a high
impedance source. This source has a nominal Thevenin
equivalent voltage of 1.2V and output impedance of 100 k
X
.
By forcing the voltage on CDA the carrier detect threshold
may be adjusted. To find the voltage required for a given
threshold the following equation may be used:
V
CDA
e
244
c
V
ON
V
CDA
e
345
c
V
OFF
CARRIER DETECT TIMING ADJUSTMENT
CDT: A capacitor on Pin 4 sets the time interval that the
carrier must be present before CD goes low. It also
sets the time interval that carrier must be removed
before CD returns high. The relevant timing equations
are:
T
CDL
j
6.4
c
C
CDT
T
CDH
j
0.54
c
C
CDT
Where T
CDL
& T
CDH
are in seconds, and C
CDT
is in
m
F.
for CD going low
for CD going high
DESIGN PRECAUTIONS
Power supplies to digital systems may contain high ampli-
tude spikes and other noise. To optimize performance of the
MM74HC943 operating in close proximity to digital systems,
supply and ground noise should be minimized. This involves
attention to power supply design and circuit board layout.
Power supply decoupling close to the device is recommend-
ed. Ground loops should be avoided. For further discussion
of these subjects see the Audio/Radio Handbook published
by National Semiconductor Corporation.
5
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