参数资料
型号: MM908E621ACDWB/R2
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO54
封装: 17.90 X 7.50 MM, 0.65 MM PITCH, PLASTIC, SOIC-54
文件页数: 16/65页
文件大小: 1221K
代理商: MM908E621ACDWB/R2
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
908E621
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
ADC SUPPLY/REFERENCE PINS (VDDA/VREFH
AND VSSA/VREFL)
VDDA and VSSA are the power supply pins for the analog-
to-digital converter (ADC).
VREFH and VREFL are the reference voltage pins for the
ADC.
The supply and reference signals are internally connected.
It is recommended that a high quality ceramic decoupling
capacitor be placed between these pins.
For details refer to the 68HC908EY16 datasheet.
MCU POWER SUPPLY PINS (EVDD AND EVSS)
EVDD and EVSS are the power supply and ground pins.
The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-
duration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 datasheet.
TEST MODE PIN (TESTMODE)
This pin is for test purpose only. In the application this pin
has to be forced to GND.
For Programming/Test this pin has to be forced to VDD to
bring the analog die into Test mode. In Test mode the Reset
Timeout (80ms) is disabled and the LIN receiver is disabled
NOTE: After detecting a RESET (internal or external), the
PSON bit needs to be set within 80ms. If not, the device will
automatically enter sleep mode.
MCU TEST PIN (FLSVPP)
This pin is for test purposes only. This pin should either be
left open (not connected) or can be connected to GND.
NO CONNECT PINS (NC)
The NC pins are not connected internally.
Note: Each of the NC pins can be left open or connected
to ground (recommended).
EXPOSED PAD PIN
The exposed pad pin on the bottom side of the package
conducts heat from the chip to the PCB board. For thermal
performance, the pad must be soldered to the PCB board. It
is recommended that the pad be connected to the ground
potential.
4,7F
0,1F
VDDA/VREFH
EVDD
EVSS
VSSA/VREFL
VDD
VSS
C
Analog
Die
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