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参数资料
| 型号： | MM908E626AVEK |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 15/43页 |
| 文件大小： | 0K |
| 描述： | IC STEPPER MOTOR DRIVER 54-SOIC |
| 标准包装： | 26 |
| 应用： | 自动镜像控制 |
| 核心处理器： | HC08 |
| 程序存储器类型： | 闪存（16 kB） |
| 控制器系列： | 908E |
| RAM 容量： | 512 x 8 |
| 接口： | SCI，SPI |
| 输入/输出数： | 13 |
| 电源电压： | 8 V ~ 18 V |
| 工作温度： | -40°C ~ 115°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 54-BSSOP（0.295"，7.50mm 宽）裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 54-SOICW-EP |
| 产品目录页面： | 808 (CN2011-ZH PDF) |
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Analog Integrated Circuit Device Data
22
Freescale Semiconductor
908E626
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) creates the
communication link between the microcontroller and the
908E626.
The interface consists of four pins (see Figure 11):
SS—Slave Select
MOSI—Master-Out Slave-In
MISO—Master-In Slave-Out
SPSCK—Serial Clock (maximum frequency 4.0 MHz)
A complete data transfer via the SPI consists of 2 bytes.
The master sends address and data, slave system status,
and data of the selected address.
Figure 11. SPI Protocol
During the inactive phase of SS, the new data transfer is
prepared. The falling edge on the SS line indicates the start
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
The MISO output changes data on a rising edge of
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of SS.
After a write operation, the transmitted data is latched into
the register by the rising edge of SS. Register read data is
internally latched into the SPI at the time when the parity bit
is transferred. SS HIGH forces MISO to high-impedance.
MASTER ADDRESS BYTE
A4:A0
Contains the address of the desired register.
R/W
Contains information about a read or a write operation.
If R/W = 1, the second byte of master contains no valid
information, slave just transmits back register data.
If R/W = 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the SMARTMOS register on rising edge of
SS
.
Parity P
The parity bit is equal to “0” if the number of 1 bits is an
even number contained within R/W, A4:A0. If the number of
1 bits is odd, P equals “1”. For example, if R/W = 1, A4:A0 =
00001, then P equals “0.”
The parity bit is only evaluated during a write operation.
Bit X
Not used.
Master Data Byte
Contains data to be written or no valid data during a read
operation.
S7
S6
S5
S4
S3
S2
S1
S0
R/W
A4
A3
A2
A1
A0
P
X
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
System Status Register
Read/Write, Address, Parity
Data (Register write)
Data (Register read)
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
SS
MOSI
MISO
SPSCK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MM908E626AVPEK | 功能描述:8位微控制器 -MCU MCU + LIN + MOTOR DRIVER RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MM908E626AVPEKR2 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MM908E626R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication |
| MM-90N | 功能描述:ANT MAGN MNT VEHIC 3.5"DIA 10'NF RoHS:是 类别:RF/IF 和 RFID >> RF 天线 系列:* 标准包装:1 系列:* |
| MM90R9F | 制造商:Ohmite Mfg Co 功能描述: |
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