参数资料
型号: MMA5224W
厂商: Freescale Semiconductor
文件页数: 31/58页
文件大小: 0K
描述: IC ACCELER 240G X-AXIS 16QFN
标准包装: 75
轴: X
加速范围: ±240g
灵敏度: 8LSB/g,4LSB/g,2LSB/g,1LSB/g
电源电压: 4.2 V ~ 17 V
输出类型: 数字
带宽: 400Hz
接口: SPI
安装类型: 表面贴装
封装/外壳: 16-QFN 裸露焊盘
供应商设备封装: 16-QFN(6x6)
3.5.3.4
Offset Monitor
The device includes an offset monitor circuit. The output of the single pole low-pass filter in the offset cancellation block is
continuously monitored against the offset limits specified in Section 2.4 . An up/down counter is employed to count up If the output
exceeds the limits, and to count down if the output is within the limits. The output of the counter is compared against the count
limit OFFMON CNTLIMIT . If the counter exceeds the limit, the OFF_B flag in the SC register is cleared. The counter rails once the
max counter value is reached (OFFMON CNTSIZE ). The offset monitor is disabled during Initialization Phase 1, Phase 2, and
Phase 3.
3.5.3.5
Data Interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital
signal processing chain is delayed one sample time. On detection of a sync pulse the transmitted data is interpolated from the
two previous samples, resulting in a latency of one sample time, and a maximum signal jitter of ±1/16 of a sample time. Reference
Section 4.5 for more information regarding interpolation and data latency.
3.5.3.6
Output Scaling
The 26-bit digital output from the DSP is clipped and scaled to a 10-bit or 8-bit word which spans the acceleration range of the
device. Figure 22 shows the method used to establish the output acceleration data word from the 26-bit DSP output.
Over Range
Signal
Noise
Margin
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
...
D2
D1
D0
8-bit Data Word
D21
D20
D19
D18
D17
D16
D15
D14
Using Rounding
10-bit Data Word
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
Using Rounding
Figure 22. 10-Bit Output Scaling Diagram
3.5.3.7
PCM Output Function
The device provides the option for a PCM output function. The PCM output is activated if the PCM bit is set in the DEVCFG2
register. When the PCM function is enabled, a 4 MHz Pulse Code Modulated signal proportional to the upper 9 bits of the 10-bit
acceleration response is output onto the PCM pin. The PCM output is intended for test use only.
D[21:13]
Output Scaling
9
A
CARRY
PCM
D FF Q Q
FF Q
FF
FF
FF
Q Q
CLK
Q Q
CLK
Q Q
CLK
Q Q
CLK
Section 3.5.3.6
Sample updated every 16 μ S
9 Bit ADDER
B SUM
f CLK = 4 MHz
9
9
D D Q Q
D D Q Q
D D Q Q
FF
FF
FF
CLK FF
CLK
CLK
CLK
CLK Q
Figure 23. PCM Output Function Block Diagram
MMA52xxKW
Sensors
Freescale Semiconductor, Inc.
31
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