参数资料
型号: MMA5248WR2
厂商: Freescale Semiconductor
文件页数: 19/58页
文件大小: 0K
描述: IC ACCELER 480G X-AXIS 16QFN
标准包装: 1,000
轴: X
加速范围: ±480g
灵敏度: 8LSB/g,4LSB/g,2LSB/g,1LSB/g
电源电压: 4.2 V ~ 17 V
输出类型: 数字
带宽: 400Hz
接口: SPI
安装类型: 表面贴装
封装/外壳: 16-QFN 裸露焊盘
供应商设备封装: 16-QFN(6x6)
3.1.7
Manufacturer ID (MFG_ID)
The manufacturer ID register is a user programmable OTP register that contains the PSI5 manufacturer ID. The manufacturer
ID register has no impact on the performance, but is transmitted during the PSI5 initialization phase 2 in 10-bit mode.
Location
Bit
Address
$0D
Register
MFG_ID
7
MFG_ID[7]
6
MFG_ID[6]
5
MFG_ID[5]
4
MFG_ID[5]
3
MFG_ID[3]
2
MFG_ID[2]
1
MFG_ID[1]
0
MFG_ID[0]
Factory Default
0
0
0
0
0
0
0
0
MFG_ID
0000 0000
Other
PSI5 Init Data Transmission (D$, D5)
Reference Table 10
D4 = 0100
D5 = 0110
D4 = MFG_ID[7:4]
D5 = MFG_ID[3:0]
3.2
3.2.1
OTP Array Error Detection
Factory Programmed OTP Array CRC Verification
The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC verification is enabled only when the
factory programmed array is locked. The CRC verification uses a generator polynomial of g(x) = X 3 + X + 1, with a seed
value = ‘111’.
Once the CRC verification is enabled, the CRC is continuously calculated on all bits in registers $00, $01, $02, $03, and $04
and on the factory programmable device configuration bits with the exception of the factory lock bit. Bits are fed in from right to
left (LSB first), and top to bottom (lower addresses first) in the register map. The calculated CRC is then compared against the
stored 3 bit CRC. If a CRC error is detected in the OTP array, the IDEF_B bit is cleared in the SC register.
The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array val-
ues.
3.2.2
User Programmable OTP Array Error Detection
The user programmable OTP array is independently verified for errors. The Error Detection is enabled only when the LOCK_U
bit in the user data register array is set.
When a PSI5 Programming Mode “Execute Programming of NVM” command is received and the LOCK_U bit is set, the device
calculates the error detection code and writes the code to NVM, enabling the Error Detection.
Once the error detection is enabled, the error detection code is continuously calculated on all bits in registers $05, $06, $07,
$08, $09, $0A, $0B and $0D with the exception of the LOCK_U bit. The calculated code is then compared against the stored
error code. If a mismatch is detected, the IDEN_B bit is cleared in the SC register.
The error detection is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.
MMA52xxKW
Sensors
Freescale Semiconductor, Inc.
19
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