参数资料
型号: MN101DF06K
厂商: PANASONIC CORP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 14.32 MHz, MICROCONTROLLER, PQFP100
封装: 18 X 18 MM, PLASTIC, QFP-100
文件页数: 3/4页
文件大小: 54K
代理商: MN101DF06K
108
Electrical Characteristics
Supply current
Limit
Symbol
Condition
min
typ
max
Unit
Parameter
IDD1
14.32 MHz operation without load, VDD = 5 V
60
100
mA
IDD2
1/1024 of 14.32 MHz operation without load, VDD = 3.0 V
2
5
mA
IDD3
Stop of 14.32 MHz oscillation, VDD = 2.7 V
50
100
A
32 kHz oscillation operation without load
IDSP
Stop of oscillation without load, VDD = 5 V
0
20
A
IDHT0
14.32 MHz oscillation without load, VDD = 5 V
5
15
mA
IDHT1
Stop of 14.32 MHz oscillation, VDD = 2.7 V
520
A
32 kHz oscillation operation without load
(Ta = 25
°C ± 2°C , VSS = 0 V)
Operating supply current
Supply current at STOP
Supply current at HALT
A/D Converter Performance
Limit
Symbol
Condition
min
typ
max
Unit
Parameter
NLAD
± 3
LSB
tAD
fosc = 14.32 MHz
8
s
05
V
(Ta = 25
°C ± 2°C , VDD = 5.0 V , VSS = 0 V)
Conversion relative error
A/D Conversion Time
Analog Input Voltage
XDS
Built-in U.S. closed caption data slicer (optional 2 line data can be extracted.)
ROM Correction
Correcting address designation: up to 3 addresses possible
Correction method: correction program being saved in internal RAM
I/O Pins
75
Common use: 75 ports 0, 1, 2, 4, 5, 6, 7, A, B (by bit)
I/O
2
Common use: 2
Input
A/D Inputs
8-bit
× 13-ch. (without S/H)
PWM
13-bit
× 2-ch. (at repetition cycle 572 s, 14.32 MHz),
10-bit
× 2-ch. (at repetition cycle 71.5 s, 14.32 MHz), 8-bit × 1-ch. (at repetition cycle 35.7 s, 14.32 MHz)
ICR
18-bit
× 6-ch.
OCR
16-bit
× 7-ch. , 8-bit × 1-ch.
Special Ports
Buzzer output; 3-state output (PTO) VLP pin; synchronous output: 7; 3-state synchronous output: 4;
remote control receive; CTL amp; built-in FG amp;
output of 1/2 OSC oscillation clock (2 V[p-p]); output of 1/4 OSC oscillation clock (1 V[p-p])
Notes
VISS/VASS detection function
MAD00029BEM
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