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参数资料
| 型号： | MN101DP02JAC |
| 厂商： | PANASONIC CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 14.32 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 18 X 18 MM, PLASTIC, QFP-100 |
| 文件页数： | 2/4页 |
| 文件大小： | 53K |
| 代理商： | MN101DP02JAC |
103
MN101D02D , MN101D02F , MN101D02G
MN101D02H
Serial Interface (Continue)
Serial 2: 8-bit
× 1 (I2C) (master transmission/reception, slave transmission/reception)
Clock source 1/72, 1/80, 1/84, 1/96, 1/102, 1/112, 1/128, 1/144, 1/160, 1/168,
1/192, 1/224, 1/256, 1/320 of system clock; SCK pin input
OSD
Accommodation with menu or super impose display
Applicable broadcasting system
: NTSC, PAL, PAL-M, PAL-N
Screen configuration
: 24 characters
× 2n rows (n = 1 to 6)
Character type
: max. 512 character types (variable)
Character size
: 12
× 18 dots
Enlarged characters
: each
× 2, × 3 or × 4 settings in horizontal and vertical
Character interpolation
: none
Background color
: 8-hue settable (settable in the row unit at menu display)
Background intensity
: 8 gradations settable in the row unit
Character color
: white
Character intensity
: 8 gradations settable in the row unit
Frame function
: 1-dot frame in 4 or 8 directions
Frame intensity
: 4 gradations settable in the row unit
Box shade function
: settable in the character unit (only at composite output with 128 character
types or more)
Blinking
: none (covered by software)
Inverted character
: settable in the character unit
Halftone
: settable in the row unit in 2 intensity gradations (setting in the row unit)
Input
: composite video signal input (output level: 1 V[p-p] / 2 V[p-p])
Clamp method
: sync chip clamp, clamp level in 4 levels
Output
: composite video output
: digital output (6 pins)
8 character and background colors each settable at digital output.
Measure against image fluctuation : built-in AFC circuit
Sync signal detection function
: detection functions for horizontal and vertical sync signals (integral system)
with horizontal sync signal interpolation function
XDS
Built-in U.S. closed caption data slicer (optional 2 line data can be extracted.)
ROM Correction
Correcting address designation: up to 2 addresses possible
Correction method: correction program being saved in internal RAM
I/O Pins
73
Common use: 73 ports 0, 1, 2, 4, 5, 6, 7, A, B (by bit)
I/O
4
Common use: 4
Input
A/D Inputs
8-bit
× 12-ch. (without S/H)
PWM
13-bit
× 2-ch. (at repetition cycle 572 s, 14.32 MHz),
10-bit
× 2-ch. (at repetition cycle 71.5 s, 14.32 MHz),
14-bit
× 1-ch. (at repetition cycle 1144 s, 14.32 MHz)
ICR
18-bit
× 6-ch.
OCR
16-bit
× 7-ch. , 8-bit × 1-ch.
Special Ports
Buzzer output; 3-state output (PTO) VLP pin; synchronous output: 7; 3-state synchronous output: 4;
remote control receive; CTL amp; built-in FG amp;
output of 1/2 OSC oscillation clock (2 V[p-p]); output of 1/4 OSC oscillation clock (1 V[p-p])
Notes
VISS/VASS detection function
See the next page for electrical characteristics, pin assignment and support tool.
MAD00028BEM
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相关代理商/技术参数 |
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| MN101E01J | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:MN101E01J |
| MN101E01K | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:MN101E01J |
| MN101E01L | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:MN101E01K |
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