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参数资料
| 型号： | MN103SF33N |
| 厂商： | PANASONIC CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, MROM, 41 MHz, MICROCONTROLLER, CBGA360 |
| 封装： | 13 X 13 MM, LEAD FREE, CERAMIC, MBGA-360 |
| 文件页数： | 1/3页 |
| 文件大小： | 104K |
| 代理商： | MN103SF33N |
MN103S33N
Data RAM (
×××××32-bit)
24 K-byte
Command ROM (
×××××64-bit)
512 K-byte
Type
MN103S33N
Package
MBGA360-C-1313A *Lead-free
Minimum Instruction
Execution Time
24.3 ns (at 2.3 V to 2.7 V, 41 MHz)
Interrupts
RESET IRQ
× 15 NMI Key input Timer × 44 Input capture × 16 PWM × 8 SIF × 25
DMA
× 12 WDT A/D System error
Timer Counter
8-bit timer
× 12
Reload-down count
Cascade connection possible (usable as a 16-bit to 32-bit timer)
8-bit timer with PWM
× 8
Reload-down count
Cascade connection possible (usable as a 16-bit to 32-bit timer)
PWM generating function
16-bit timer
× 6
Up-down count
Input capture function
PWM generating function
Compare/capture register 2-ch.
16-bit timer
× 6
Reload-down count
Watchdog timer
× 1
DMA Controller
Number of channels: 4
Unit of transfer: 8/16/32 bits
Max. Transfer cycles: 65535
Staring factor: external interrupt, timer factor, PWM factor, serial transmission/reception factor,
A/D conversion finish, software factor
Transfer method: 2-bus cycle transfer
Adressing modes: fixed, increment, decrement
Transfer modes: word transfer, burst transfer, intermittent transfer
Serial Interface
Serial 0, 1, 3 to 8, A, B: start-stop synchronization/synchronization/I2C commonly used, 10 lines
Serial 2, 9: 2 lines for start-stop synchronization only, serial 2: 10 bytes containing receive FIFO
I/O Pins
169
Common use
I/O
25
Common use
Input
A/D Inputs
10-bit
× 25-ch.
PWM
12-, 14-bit resolution
× 5-ch.
output waveform value load control function provided 16-bit resolution
× 2-ch.
ICR
28-bit
× 13-ch. + 16-bit × 6-ch. (common with timer)
OCR
16-bit
× 12-ch. (common with timer)
Timer Synchronous Output
4-bit (synchronous output)
× 2-ch.
MAF00005GEM
ROM Collection
4-ch.
264
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