参数资料
型号: MOBILE AMD-K6-III-P
厂商: Advanced Micro Devices, Inc.
英文描述: 32 Bit Processor with TriLevel Cache Design and Superscalar MMX Unit(带三级缓存和超标量MMX单元的32位处理器)
中文描述: 32位处理器TriLevel高速缓存的设计和超标量MMX公司股(带三级缓存和超标量MMX公司单元的32位处理器)
文件页数: 15/106页
文件大小: 2007K
代理商: MOBILE AMD-K6-III-P
Chapter 1
Mobile AMD-K6
-
III
-P Processor
1
22655C/0—September 1999
Mobile AMD-K6
-
III
-P Processor Data Sheet
Preliminary Information
1
Mobile AMD-K6
-
III
-P Processor
I
Advanced 6-Issue RISC86
Superscalar Microarchitecture
Ten parallel specialized execution units
Multiple sophisticated x86-to-RISC86 instruction decoders
Advanced two-level branch prediction
Speculative execution
Out-of-order execution
Register renaming and data forwarding
Issues up to six RISC86 instructions per clock
TriLevel Cache Design
Large On-Chip Split 64-Kbyte Level-One (L1) Cache
32-Kbyte instruction cache with additional predecode cache
32-Kbyte writeback dual-ported data cache
On-die 256-Kbyte full processor speed, backside Level-Two (L2) Cache
Support for external Level-Three (L3) Cache on 100-MHz frontside bus
MESI protocol support
High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit
Superscalar MMX unit supports industry-standard MMX instructions
3DNow! Technology for high-performance multimedia and 3D graphics
capabilities
Compatible with Super7
100-MHz frontside bus or Socket 7 66-MHz notebook
design
Socket 7-Compatible Ceramic Pin Grid Array (CPGA) Package
Industry-Standard System Management Mode (SMM)
IEEE 1149.1 Boundary Scan
x86 Binary Software Compatibility
Low Voltage 0.25-Micron Process Technology
21.3 Million Transistors
The Mobile AMD-K6
-III-P
processor is AMD’s third generation mobile AMD-K6
processor delivering the highest performance yet for x86 notebook PC systems. The
Mobile AMD-K6-III-P processor is based on the advanced Mobile AMD-K6-2 core and
adds AMD's unique TriLevel Cache design for enhanced system performance. The
TriLevel Cache design provides a large 64-Kbyte L1 cache, a 256-Kbyte L2 cache
operating at full processor speed on a backside bus, and up to 1 Mbyte of available L3
cache memory on the external 100-MHz frontside bus. This combination of the largest
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相关PDF资料
PDF描述
MOBILE AMD-K6 32 Bit Microprocessor With 64-K Byte Level-one Cache and Advanced RISC86 Superscalar Microarchitecture(32位微处理器带64K字节高速缓存和高级的RISC86超标量微体系结构)
MP028F036M12AL PRM Regulator 28 Vdc Input
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