- 您现在的位置：买卖IC网 > PDF目录378673 > MPC185TS (Motorola, Inc.) Security Processor PDF资料下载
参数资料
| 型号： | MPC185TS |
| 厂商： | Motorola, Inc. |
| 英文描述： | Security Processor |
| 中文描述： | 安全处理器 |
| 文件页数： | 6/12页 |
| 文件大小： | 227K |
| 代理商： | MPC185TS |
6
MPC185 Security Processor Technical Summary
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
6.2 The MPC185 Controller
The MPC185 controller manages on-chip resources, including the individual execution units (EUs), FIFOs,
the 60x Interface, and the internal buses that connect all the various modules. The controller receives service
requests from the 60x interface and various crypto-channels, and schedules the required activities. The
controller can configure each of the on-chip resources in three modes:
Host-controlled mode—The host is directly responsible for all data movement into and out of the
resource.
Static mode—The user can reserve a specific execution unit to a specific crypto-channel.
Dynamic mode—A crypto channel can request a particular service from any available execution
unit.
6.3 Host-Managed Register Access
All EUs can be used entirely through register read/write access. It is strongly recommended that read/write
access only be performed on a EU that is statically assigned to an idle crypto-channel. Such an assignment
is the only method for the host to inform the controller that a particular EU is in use.
6.4 Static EU Access
The controller can be configured to reserve one or more EUs to a particular crypto-channel. Doing so
permits locking the EU to a particular context. When in this mode, the crypto-channel can be used by
multiple descriptors representing the same context without unloading and reloading the context at the end
of each descriptor. This mode presents considerable performance improvement over dynamic access, but
only when the MPC185 is supporting few (or one) contexts.
Static EU access can also be used to reserve one particular Public Key Execution Unit (PKEU) for one type
of computation. For example, one PKEU could be reserved for all private key RSA operations using prime
P, and the other could be reserved for all computations using prime Q. Again, this presents a performance
improvement because all fixed parameters can remain within the reserved PKEUs. This reduces the
overhead of loading and unloading contexts and therefore improves performance. However, this is only a
performance improvement if the lack of dynamically available PKEUs does not become a bottleneck in key
agreement protocols.
6.5 Dynamic EU Access
Processing begins when a data packet descriptor pointer is written to the Next Descriptor Pointer Register
of one of the crypto-channels. Prior to fetching the data referred to by the descriptor and based on the
services requested by the descriptor header in the descriptor buffer, the controller dynamically reserves
usage of an EU to the crypto-channel. If all appropriate EUs are already dynamically reserved by other
crypto-channels, the crypto-channel stalls and waits to fetch data until an appropriate EU is available.
If multiple crypto-channels simultaneously request the same EU, the EU is assigned on a weighted priority
or round-robin basis. Once the required EU has been reserved, the crypto-channel fetches and loads the
appropriate data packets, operates the EU, unloads data to system memory, and releases the EU for use by
another crypto-channel. If a crypto-channel attempts to reserve a statically-assigned EU (and no appropriate
EUs are available for dynamic assignment), an interrupt is generated and status indicates illegal access.
When dynamic assignment is used, each encryption/decryption packet must contain context that is
particular to the context being supported.
F
Freescale Semiconductor, Inc.
n
.
相关PDF资料 |
PDF描述 |
|---|---|
| MPC2001 | 256KB Asynchronous Secondary Cache Module for PowerPC |
| MPC2001SG12 | 256KB Asynchronous Secondary Cache Module for PowerPC |
| MPC2001SG15 | 256KB Asynchronous Secondary Cache Module for PowerPC |
| MPC2004 | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| MPC2005 | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC18730EP | 功能描述:线性稳压器 - 标准 POWER MGT IC RoHS:否 制造商:STMicroelectronics 输出类型: 极性: 输出电压:1.8 V 输出电流:150 mA 负载调节: 最大输入电压:5.5 V 线路调整率: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SOT-323-5L |
| MPC18730EP | 制造商:Freescale Semiconductor 功能描述:IC POWER MANAG PROG 121MA 64QFN |
| MPC18730EP/R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Power Management IC with Five Power Management IC with Five Power Management IC with Five Power Management IC with Five |
| MPC18730EPR2 | 功能描述:板上安装压力/力传感器 POWER MGT IC RoHS:否 制造商:Honeywell 工作压力:0 bar to 4 bar 压力类型:Gage 准确性:+ / - 0.25 % 输出类型:Digital 安装风格:Through Hole 工作电源电压:5 V 封装 / 箱体:SIP 端口类型:Dual Radial Barbed, Same sides |
| MPC18A26VMEL | 制造商:Motorola Inc 功能描述: |
发布紧急采购，3分钟左右您将得到回复。