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| 型号： | MPC5200VR400BR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 9/72页 |
| 文件大小： | 0K |
| 描述： | IC MPU 32BIT 400MHZ 272-PBGA |
| 标准包装： | 500 |
| 系列： | MPC52xx |
| 核心处理器： | e300 |
| 芯体尺寸： | 32-位 |
| 速度： | 400MHz |
| 连通性： | CAN，EBI/EMI，以太网，I²C，IrDA，J1850，SPI，UART/USART，USB |
| 外围设备： | AC'97，DMA，I²S，POR，PWM，WDT |
| 输入/输出数： | 56 |
| 程序存储器类型： | 外部程序存储器 |
| RAM 容量： | 16K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.42 V ~ 1.58 V |
| 振荡器型： | 内部 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 272-BBGA |
| 包装： | 带卷 (TR) |
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MPC5200B Data Sheet, Rev. 4
Freescale Semiconductor
17
2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt
sources. Take care of interrupt prioritization which may increase the latencies.
Because all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has
to exceed a minimum pulse width of more than one IP_CLK cycle.
NOTES:
1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200B User’s Manual
(MPC5200BUM) for further information.
2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second
interrupt is not recognized at all.
Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt
service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended
to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design
and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.
1.3.6
SDRAM
1.3.6.1
Memory Interface Timing-Standard SDRAM Read Command
Table 17. Minimum Pulse Width for External Interrupts to be Recognized
Name
Min Pulse Width
Max Pulse Width
Reference Clock
SpecID
All external interrupts (IRQs, GPIOs)
> 1 clock cycle
—
IP_CLK
A4.22
Table 18. Standard SDRAM Memory Read Timing
Sym
Description
Min
Max
Units
SpecID
tmem_clk
MEM_CLK period
7.5
—
ns
A5.1
tvalid
Control Signals, Address and MBA Valid after
rising edge of MEM_CLK
—tmem_clk ×0.5 +0.4
ns
A5.2
thold
Control Signals, Address and MBA Hold after
rising edge of MEM_CLK
tmem_clk ×0.5
—
ns
A5.3
DMvalid
DQM valid after rising edge of MEM_CLK
—
tmem_clk ×0.25 + 0.4
ns
A5.4
DMhold
DQM hold after rising edge of MEM_CLK
tmem_clk ×0.25 – 0.7
—ns
A5.5
datasetup
MDQ setup to rising edge of MEM_CLK
—
0.3
ns
A5.6
datahold
MDQ hold after rising edge of MEM_CLK
0.2
—
ns
A5.7
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