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参数资料
| 型号： | MPC5553MVF80 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PBGA208 |
| 封装： | 17 X 17 MM, 1 MM PITCH, MO-151AAF-1, MAPBGA-208 |
| 文件页数： | 40/68页 |
| 文件大小： | 1261K |
| 代理商： | MPC5553MVF80 |
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Electrical Characteristics
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Freescale Semiconductor
45
3.14
Fast Ethernet AC Timing Specifications
Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic
(TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC
signals are independent of the system clock frequency (part speed designation).
3.14.1
MII FEC Receive Signal Timing
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK
The receive functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz plus one percent.
There is no minimum frequency requirement. The processor clock frequency must exceed four times the
FEC_RX_CLK frequency.
Table 28 lists MII FEC receive channel timings.
Figure 28. MII FEC Receive Signal Timing Diagram
Table 28. MII FEC Receive Signal Timing
Spec
Characteristic
Min.
Max
Unit
1
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
5
—
ns
2
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
5
—
ns
3
FEC_RX_CLK pulse-width high
35%
65%
FEC_RX_CLK period
4
FEC_RX_CLK pulse-width low
35%
65%
FEC_RX_CLK period
1
2
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
3
4
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages
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