参数资料
型号: MPC555LFMZP40
厂商: Freescale Semiconductor
文件页数: 8/12页
文件大小: 0K
描述: IC MCU 32BIT 40MHZ 272-BGA
标准包装: 40
系列: MPC5xx
核心处理器: PowerPC
芯体尺寸: 32-位
速度: 40MHz
连通性: CAN,EBI/EMI,SCI,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 101
程序存储器容量: 448KB(448K x 8)
程序存储器类型: 闪存
RAM 容量: 26K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 32x10b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 272-PBGA
包装: 托盘
配用: MPC555CMEE-ND - KIT EVAL FOR MPC555
MPC555 Product Brief
5
Key Features
1.2.10 Two CAN 2.0B Controller Modules (TouCAN)
Each TouCAN provides these features:
Full implementation of CAN protocol specification, version 2.0A and 2.0B
Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length
Global mask register for message buffers 0 to 13
Independent mask registers for message buffers 14 and 15
Programmable transmit-first scheme: lowest ID or lowest buffer number
16-bit free-running timer for message time-stamping
Low power sleep mode with programmable wake-up on bus activity
Programmable I/O modes
Maskable interrupts
Independent of the transmission medium (external transceiver is assumed)
Open network architecture
Multimaster concept
High immunity to EMI
Short latency time for high-priority messages
Low power sleep mode with programmable wakeup on bus activity
1.2.11 Queued Serial Multi-Channel Module (QSMCM)
Queued serial peripheral interface (QSPI)
— Provides full-duplex communication port for peripheral expansion or interprocessor
communication
— Up to 32 preprogrammed transfers, reducing overhead
— 160-byte queue buffer
— Programmable transfer length: from 8 to 16 bits, inclusive
— Synchronous interface with baud rate of up to system clock divided by 4
— Four programmable peripheral-select pins support up to 16 devices
— Wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals
(e.g., – serial A/D converters, I/O latches, etc.)
Two serial communications interfaces (SCI). Each SCI offers these features:
— UART mode provides NRZ format and half-or full-duplex interface
— 16 register receive buffer and 16 register transmit buffer (SCI1 only)
— Advanced error detection and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separate transmitter and receiver enable bits and double buffering of data
— Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or
a new address byte is received
— External source clock for baud generation
— Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete
inputs, allowing realization of a low-speed serial protocol
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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