参数资料
型号: MPC5566MVR132
厂商: Freescale Semiconductor
文件页数: 58/66页
文件大小: 0K
描述: MCU 3MB FLASH 132MHZ 416-PBGA
标准包装: 200
系列: MPC55xx Qorivva
核心处理器: e200z6
芯体尺寸: 32-位
速度: 132MHz
连通性: CAN,EBI/EMI,以太网,SCI,SPI
外围设备: DMA,POR,PWM,WDT
输入/输出数: 256
程序存储器容量: 3MB(3M x 8)
程序存储器类型: 闪存
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.35 V ~ 1.65 V
数据转换器: A/D 40x12b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 416-BBGA
包装: 托盘
Revision History for the MPC5566 Data Sheet
MPC5566 Microcontroller Data Sheet, Rev. 3
Freescale
61
Table 9, DC Electrical Specifications:
Spelled out meaning of the slash ‘/’ as ‘and’ as well as ‘I/O’ as ‘input/output.’ Sentence still very confusing.
Deleted ‘input/output’ from the specs to improve clarity.
Spec 20, column 2, Characteristics,’ Slow and medium output high voltage (IOH_S = –2.0 mA):’
Created a left-justified second line and moved ‘IOH_S = –2.0 mA’ from the 1st line to the second line and deleted
the parentheses. Created a left-justified third line that reads ‘IOH_S = –1.0 mA.’
Spec 20, column 4, Min: Added a blank line before and after ‘0.80
VDDEH’ and put ‘0.85 VDDEH’ on the last line.
Spec 22, column 2, ’Slow and medium output low voltage (IOL_S = 2.0 mA):’ Created a left-justified second line
and moved ‘IOL_S = 2.0 mA.’ from the 1st line to the second line and deleted the parentheses. Created a
left-justified third line that reads ‘IOL_S = 1.0 mA.’
Spec 22, column 5, Max: Added a blank line before and after ‘0.20
VDDEH’ and put ‘0.15 VDDEH’ on the last
line.
Spec 26: Changed ‘AN[12]_MA[1]_SDO’ to ‘AN[13]_MA[1]_SDO’.
Added footnote 10 to specs 27a, b, and c on the 4-way cache line that reads: Four-way cache enabled
(L1CSR0[CORG] = 0b1) or (L1CSR0[CORG] = 0b0 with L1CSR0[WAM] = 0b1, L1CSR0[WID] = 0b1111,
L1CSR0[WDD] = 0b1111, L1CSR0[AWID] = 0b1, and L1CSR0[AWDD] = 0b1).
Added footnote 11 to specs 27a, b, and c on the max numeric values: “Preliminary. Specification pending final
characterization.”
Added footnote 12 to specs 27a, b, and c on the max TBD values: “Specification pending final characterization.”
Spec 27a: Operating current 1.5 V supplies @ 132 MHz: Changed 132 MHz to 135 MHz.
Changed maximum values for 8-way cache: All 8-way cache max values have footnote 18.
-- 1.65 typical = 630
-- 1.35 typical = 500
-- 1.65 high = 785
-- 1.35 high = 630
Changed 4-way cache with footnote 10:
-- 1.65 high = 685
-- 1.35 high = TBD with footnote 19.
Spec 27b, Operating current 1.5 V supplies @ 114 MHz:
Changed maximum values for 8-way cache. All 8-way cache max values have footnote 18:
-- 1.65 typical = 600
-- 1.35 typical = 450
-- 1.65 high = 680
-- 1.35 high = 500
Changed 4-way cache values:
-- 1.65 high = TBD with footnote 19
-- 1.35 high = TBD with footnote 19
Spec 27c, Operating current 1.5 V supplies @ 82 MHz:
Changed maximum values for 8-way cache: All 8-way cache max values have footnote 18.
-- 1.65 typical = 490,
-- 1.35 typical = 360,
-- 1.65 high = 520,
-- 1.35 high = 390.
Changed 4-way cache values:
-- 1.65 high = TBD with footnote 19
-- 1.35 high = TBD with footnote 19
Table 35. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0 (continued)
Location
Description of Changes
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