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| 型号： | MPC5567MVZ112 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | FLASH, 112 MHz, MICROCONTROLLER, PBGA324 |
| 封装： | 23 X 23 MM, 1 MM PITCH, LEAD FREE, PLASTIC, MS-034AAJ-1, BGA-324 |
| 文件页数： | 61/66页 |
| 文件大小： | 1903K |
| 代理商： | MPC5567MVZ112 |
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MPC5567 Microcontroller Data Sheet, Rev. 1.0
Revision History for the MPC5567 Data Sheet
Freescale Semiconductor
64
Table 16 FLASH BIU Settings vs. Frequency of Operations:
‘Added footnote 1 to the end of the table title, The footnote reads: ‘Illegal combinations exist. Use entries from
the same row in this table.’
Moved footnote 2:’ For maximum flash performance, set to 0b11’ to the ‘DPFEN’ column header.
Deleted the x-refs in the ‘DPFEN’ column for the rows.
Created a x-ref for footnote 2 and inserted in the ‘IPFEN’ column header.
Deleted the x-refs in the ‘IPFEN’ column for the rows.
Moved footnote 3:’ For maximum flash performance, set to 0b110’ to the ‘PFLIM’ column header.
Deleted the x-refs in the ‘PFLIM’ column for the rows.
Moved footnote 4:’ For maximum flash performance, set to 0b1’ to the ‘BFEN’ column header.
Deleted the x-refs in the ‘BFEN’ column for the rows.
Changed footnotes 1, 5, and 6 to become footnotes 5, 6, and 7
footnote 5
82 MHz parts allow for 80 MHz system clock + 2% frequency modulation (FM).
footnote 6 102 MHz parts allow for 100 MHz system clock + 2% FM.
footnote 7 135 MHz parts allow for 132 MHz system clock + 2% FM.
Footnote 9: added to the end of the 1st column for the 147 MHz row that reads:
Preliminary setting. Final setting pending characterization.
Table 17 Pad AC Specifications and Table 18 Derated Pad AC Specifications: The changes are identical in the tables.
Footnote 1, deleted ‘FSYS =132 MHz.’
Footnote 2, changed from ‘tested’ to ‘(not tested).’
Footnote 3, changed from ‘Out delay. . .’ to ‘The output delay. . .’,
Changed from ‘ Add a maximum of one system clock to the output delay to get the output delay with respect to
the system clock‘ to ‘To calculate the output delay with respect to the system clock, add a maximum of one system
clock to the output delay.’
Footnote 4: changed ‘Delay’ to ‘The output delay.’
Footnote 5: deleted ‘before qualification.’
Changed from ‘This parameter is supplied for reference and is not guaranteed by design and not tested’ to ‘This
parameter is supplied for reference and is guaranteed by design and tested.’
Table 19 Reset and Configuration Pin Timing: Footnote 1, deleted ‘FSYS = 132 MHz,’ and ‘VDD = 1.35–1.65.’
Table 20 JTAG Pin AC Electrical Characteristics:
Footnote 1, deleted: ‘, and CL = 30 pF with DSC = 0b10, SRC = 0b11’
Footnote 1, changed ‘functional’ to ‘Nexus.’
Table 21 Nexus Debug Port Timing.
Changed Spec 12, TCK Low to TDO Data Valid: Changed ‘VDDE = 3.0 to 3.6 volts’ maximum value in column 4
from 9 to 10. Now reads ‘VDDE = 3.0–3.6 V’ with a max value of 10.
Table 22 Bus Operation Timing:
External Bus Frequency in the table heading: Added footnote that reads: Speed is the nominal maximum
frequency. Max speed is the maximum speed allowed including frequency modulation (FM). 82 MHz parts allow
for 80 MHz system clock + 2% FM; 114 MHz parts allow for 112 MHz system clock + 2% FM, and 135 MHz parts
allow for 132 MHz system clock + 2% FM.
Spec 1: Changed the values in Min. columns: 40 MHz from 25 to 24.4; 56 MHz from 17.9 to 17.5, and the
66 MHz from 15.2 to 14.9.
Specs 5 and 6: CLKOUT positive edge to output signals invalid of high: Corrected format to show the bus timing
values for various frequencies with EBTS bit = 0 and EBTS bit = 1.
Specs 5, and 6: Deleted the BG, BR, and TSIZ[0:1] signals for arbitration. Added the following calibration signals:
CAL_ADDR[10:30], CAL_CS[0, 2:3], CAL_DATA[0:15], CAL_OE, CAL_RD_WR, CAL_TS, CAL_WE/BE[0:1].
Specs 7 and 8: Deleted the BG, BR, and TSIZ[0:1] signals for arbitration. Added the following calibration signals:
CAL_ADDR[10:30], CAL_DATA[0:15], CAL_RD_WR, and CAL_TS.
Table 33. Table and Figure Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Changes
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MPC551x
and
MPC5533
products
in
208
MAPBGA
packages;
MPC5534
and
MPC5553
products
in
208
and
496
MAPBGA
packages;
MPC5554,
MPC5565,
MPC5566
and
MPC5567
products
in
496
MAPBGA
packages
相关PDF资料 |
PDF描述 |
|---|---|
| MPC5567MVZ132 | FLASH, 132 MHz, MICROCONTROLLER, PBGA324 |
| MPC5567MZP112 | FLASH, 112 MHz, MICROCONTROLLER, PBGA416 |
| MPC5567MZP132 | FLASH, 132 MHz, MICROCONTROLLER, PBGA416 |
| MPC5567MZP80 | FLASH, 80 MHz, MICROCONTROLLER, PBGA416 |
| MK2762-01SLFTR | 33.333 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC5567MVZ112R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MVZ132 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MVZ132R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MVZ80 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MVZ80R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Microcontroller |
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