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| 型号： | MPC5604PEF0VLL4 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT LQFP-100 |
| 文件页数： | 72/99页 |
| 文件大小： | 1130K |
| 代理商： | MPC5604PEF0VLL4 |
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MPC5604P Microcontroller Data Sheet, Rev. 7
Freescale Semiconductor
74
Table 35. RESET electrical characteristics
Symbol
C
Parameter
Conditions1
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 °C to TA MAX, unless otherwise specified
Value
Unit
Min
Typ
Max
VIH
SR P Input High Level CMOS
(Schmitt Trigger)
—
0.65VDD
—VDD+0.4
V
VIL
SR P Input low Level CMOS
(Schmitt Trigger)
—
–0.4
—
0.35VDD
V
VHYS
CC C Input hysteresis CMOS
(Schmitt Trigger)
—0.1VDD
——
V
VOL
CC P Output low level
Push Pull, IOL = 2mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0
(recommended)
—
0.1VDD
V
Push Pull, IOL = 1mA,
VDD = 5.0 V ± 10%, PAD3V5V = 1
2
2 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
device reference manual).
—
0.1VDD
Push Pull, IOL = 1mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1
(recommended)
——
0.5
ttr
CC D Output transition time
output pin3
MEDIUM configuration
3 C
L includes device and package capacitance (CPKG <5pF).
CL = 25pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
10
ns
CL = 50pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
20
CL = 100pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
40
CL = 25pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
12
CL = 50pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
25
CL = 100pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
40
WFRST SR P RESET input filtered
pulse
——
—
40
ns
WNFRST SR P RESET input not filtered
pulse
—500
—
ns
tPOR
CC D Maximum delay before
internal reset is released
after all VDD_HV reach
nominal supply
Monotonic VDD_HV supply ramp
—
1
ms
|IWPU| CC P Weak pull-up current
absolute value
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
A
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 1
4
10
—
250
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