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参数资料
| 型号： | MPC5607BF0AMLU4R |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP176 |
| 封装： | 24 X 24 MM, ROHS COMPLIANT, LQFP-176 |
| 文件页数： | 86/110页 |
| 文件大小： | 907K |
| 代理商： | MPC5607BF0AMLU4R |
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Electrical characteristics
MPC5607B Microcontroller Data Sheet, Rev. 6
Freescale Semiconductor
77
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time tS
is always much longer than the internal time constant:
Eqn. 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
2. A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time ts, a constraints on RL sizing is obtained:
Eqn. 9
Of course, RL shall be sized also according to the current limitation constraints, in combination with RS (source
impedance) and RF (filter resistance). Being CF definitively bigger than CP1, CP2 and CS, then the final voltage VA2
(at the end of the charge transfer transient) will be much higher than VA1. Equation 10 must be respected (charge
balance assuming now CS already charged at VA1):
Eqn. 10
The two transients above are not influenced by the voltage source that, due to the presence of the RFCF filter, is not able to
provide the extra charge to compensate the voltage drop on CS with respect to the ideal source VA; the time constant RFCF of
the filter is very high with respect to the sampling time (ts). The filter is typically designed to act as antialiasing.
1 RSW RAD
+
=
CP CS
CP CS
+
---------------------
1 RSW RAD
+
CS ts
VA1 CS CP1 CP2
++
VA CP1 CP2
+
=
2 RL
CS CP1 CP2
++
10
2
10 RL CS CP1 CP2
++
=
ts
VA2 CS CP1 CP2 CF
++
+
VA CF
VA1
+CP1 CP2
+CS
+
=
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