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| 型号： | MPC603PRX160LX |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 160 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件页数： | 39/40页 |
| 文件大小： | 431K |
| 代理商： | MPC603PRX160LX |
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8
PID7v-603e Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 6. Clock AC Timing Specifications
Vdd = AVdd = 2.5
± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc, 0 ≤ Tj ≤ 105 °C
Num
Characteristic
160 MHz
166 MHz
180 MHz
200 MHz
220, 225
MHz
233, 240
MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Processor
frequency
125
160
125
167
125
180
125
200
125
220,
225
125
233,
240
MHz 1
VCO
frequency
250
320
250
333
250
360
250
400
250
440,
450
250
466,
480
MHz 1
SYSCLK
frequency
25
66.67
25
66.67
25
66.67
25
66.67
25
75
25
75
MHz 1
1
SYSCLK cycle
time
15
40.0
15
40.0
15
40.0
15
40.0
13.3
40.0
13.3
40.0
ns
2,3
SYSCLK rise
and fall time
—
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
2.0
ns
2
4
SYSCLK duty
cycle measured
at 1.4 V
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
40.0
60.0
%
3
SYSCLK jitter
—
±150 —
±150 ps
4
603e internal
PLL-relock time
—
100
—
100
—
100
—
100
—
100
—
100
s
3,5
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting SYSCLK
(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or
minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in Section 1.8, “System Design
Information,” for valid PLL_CFG[0–3] settings.
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term combined) must
be under
±150 ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum
time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset
sequence. This specication also applies when the PLL has been disabled and subsequently re-enabled during
sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-
relock time (100
s) during the power-on reset sequence.
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