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参数资料
| 型号： | MPC755BZT350TD |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, PBGA360 |
| 封装： | PLASTIC, BGA-360 |
| 文件页数： | 2/2页 |
| 文件大小： | 511K |
| 代理商： | MPC755BZT350TD |
Cache and MMU Support
The MPC755/745 microprocessors have separate 32-Kbyte, physically-addressed instruction and data caches.
Both caches can be locked in part or whole to provide storage of critical data, key performance algorithms, or
code loops for fast response time. The MPC755 microprocessor’s dedicated L2 cache interface with on-chip L2
tags (up to 1MB) features support for direct-mapped SRAM mode, physically-mapped SRAM mode, a fast
(typically 1/2 core speed) interface to memory, instruction-only or data-only modes, and parity checking on both
L2 address and data.
MPC755/745 microprocessors contain separate memory management units (MMUs) for instructions and data,
supporting 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory. Both feature eight
instruction block address translation (iBAT) and eight data block address translation (dBAT) registers. Access
privileges and memory protection are controlled on block or page granularities. Large, 128-entry translation
lookaside buffers (TLBs) provide efficient physical address translation and support for virtual-memory
management on both page- and variable-sized blocks. Both hardware and software tablewalks are provided for
the TLBs.
Flexible Bus Interface
MPC755/745 microprocessors have a
64-bit data bus with 32-bit mode and a
32-bit address bus. Support is included
for burst, split and pipelined
transactions. The interface provides
snooping for data cache coherency.
Both microprocessors maintain MEI
coherency protocol in hardware,
allowing access to system memory for
additional caching bus masters, such as
DMA devices.
Contact Information
Motorola offers user’s manuals,
application notes and sample code
for all of its processors. In addition,
local support for these products is
also provided. This information can
be found at:
http://motorola.com/PowerPC/
For all other inquiries about Motorola
products, please contact the Motorola
Customer Response Center at:
Phone: 800-521-6274 or
http://motorola.com/semiconductors
PowerPC 1xx, 6xx and 7xx Part Number Key
100, 600, or 700
Series Device Number
(106, 107, 603, 740, 745,
750, 755)
XPC
755
B
PX
400
L
D
Product Code
PPC Sample
XPC XC qualified
MPC Qualified
Part/Module Modifier
A
Alpha (original)
B
DGO process
E
603 Enhanced Performance
P
Enhanced & Lower Voltage
R
603e in HiP3 process
C
2:1 (106 only)
D
5:2 (106 only)
L
Full spec all modes
Frequency
2-3 digits
Application Modifier
Bus Ratio
R105
°
T
ext. temp. (-40
° to 105°)
-or-
Application Relief
Revision
Package
FE
CQFP
RX CBGA w/o lid
PX PBGA w/o lid
ZT
PBGA w/ lid
CPU Speeds – Internal
CPU Bus Dividers
Bus Interface
Instructions per Clock
L2 Cache
Typical/Maximum
Power Dissipation
Die Size
Package
Process
Voltage
SPECint95 (estimated)
SPECfp95 (estimated)
Other Performance
Execution Units
L1 Cache
Core-to-L2 Frequency
300 and 350 MHz
PowerPC 745
300-350 MHz
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7, x7.5, x8, x10
32-bit/64-bit
3 (2 + Branch)
—
TBD
51 mm2
255 PBGA
0.22
5LM
1.8/3.3V i/o, 2.0V internal
15.7 @ 350 MHz
11.6 @ 350 MHz
641 MIPS @ 350 MHz
Integer(2), Floating-Point, Branch,
Load/Store, System Register
32 Kbyte instruction
32 Kbyte data
—
300, 350 and 400 MHz
32-bit/64-bit
3 (2 + Branch)
256, 512 Kbyte
1 Mbyte
32-Kbyte instruction
32-Kbyte data
TBD
51 mm2
1:1, 1.5:1, 2:1, 2.5:1, 3:1
360 PBGA
0.22
5LM
1.8/3.3V i/o, 2.0V internal
18.1 @ 400 MHz
12.3 @ 400 MHz
733 MIPS @ 400 MHz
Integer(2), Floating-Point, Branch,
Load/Store, System Register
x3, x3.5, x4, x4.5, x5, x5.5,
x6, x6.5, x7, x7.5, x8, x10
PowerPC 755
300-400 MHz
PowerPC 755/745 CPU Summary
2000 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola and the
are registered trademarks and AltiVec is a trademark of of Motorola, Inc. PowerPC, the PowerPC logo, PowerPC 603e, PowerPC 740 and PowerPC 750 are
trademarks of International Business Machines Corporation, used under license therefrom. This document contains information on a new product under development. Specifications and information herein are subject to change without notice.
1ATX45747-0 Printed in USA 5/00 Hibbert LITRISC-UCCJ
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