Communication Processor Module
16-340
MPC823 USER’S MANUAL
MOTOROLA
SCC2
COMMUNICATION
16
PROCESSOR
MODULE
16.9.23.5 SCC2 ETHERNET MASK REGISTER. When the SCC2 is in Ethernet mode, the
16-bit read/write SCC2 mask register is referred to as the SCC2 Ethernet mask register
(SCCM–Ethernet). Since each protocol has specific requirements, the SCCM bits are
different for each implementation. This register has the same bit formats as the
SCCE–Ethernet register. If a bit in the SCCM–Ethernet register is a 1, the corresponding
interrupt in the SCCE–Ethernet register is enabled. If the bit is zero, the corresponding
interrupt in the SCCE–Ethernet register is masked.
16.9.23.6 SCC2 ETHERNET STATUS REGISTER. Since all Ethernet mode selections are
in the GSMR_x and PSMR registers, the SCC2 Ethernet status register (SCCS–Ethernet)
is not used when the SCC2 is in Ethernet mode. The current state of the RENA and CLSN
signals can be found in port C.
16.9.23.7 SCC2 ETHERNET PROGRAMMING EXAMPLE. The following is an example
initialization sequence for the SCC2 in Ethernet mode. The CLK1 pin is used for the Ethernet
receiver and the CLK2 pin is used for the transmitter.
1. Configure the port A pins to enable the TXD1 and RXD1 pins. Write PAPAR bits 12
and 13 with ones, PADIR bits 12 and 13 with zeros, and PAODR bit 13 with zero.
2. Configure the port C pins to enable CTS2 (CLSN) and CD2 (RENA). Write PCPAR and
PCDIR bits 9 and 8 with zeros and PCSO bits 9 and 8 with ones.
3. Do not enable the RTS2 (TENA) pin yet because the pin is still functioning as RTS and
transmission on the LAN could accidentally begin.
4. Configure port A to enable the CLK1 and CLK2 pins. Write PAPAR bits 7 and 6 with
ones and PADIR bits 7 and 6 with zeros.
5. Connect the CLK1 and CLK2 pins to SCC2 using the serial interface. Write the R2CS
field in the SICR to 101 and the T2CS field to 100.
6. Connect the SCC2 to the NMSI and clear the SC2 bit in the SICR.
7. Initialize the SDMA configuration register (SDCR) to 0x0001.
8. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RX buffer
descriptor and TX buffer descriptor in the dual-port RAM. Assuming one RX buffer
descriptor at the beginning of the dual-port RAM and one TX buffer descriptor following
that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008.
9. Program the CPCR to execute the INIT RX BD PARAMETER command for this
channel.
SCCM–ETHERNET
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
RESERVED
GRA RESERVED
TXE
RXF
BSY
TXB
RXB
RESET
0
00000
R/W
R/W
ADDR
(IMMR & 0xFFFF0000) + 0xA34