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参数资料
| 型号： | MPC8245TZU350D |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352 |
| 封装： | 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, TBGA-352 |
| 文件页数： | 8/68页 |
| 文件大小： | 1143K |
| 代理商： | MPC8245TZU350D |
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MPC8245 Integrated Processor Hardware Specifications, Rev. 9
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Register settings that define each DLL mode are shown in Table 9.
The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line by increasing the time
between each of the 128 tap points in the delay line. Although this increased time makes it easier to
guarantee that the reference clock is within the DLL lock range, there may be slightly more jitter in the
output clock of the DLL; that is, the phase comparator shifts the clock between adjacent tap points. Refer
to the Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines:
Part 1, for details on DLL modes and memory design.
The value of the current tap point after the DLL locks can be determined by reading bits 6–0
(DLL_TAP_COUNT) of the DLL tap count register (DTCR, located at offset 0xE3). These bits store the
value (binary 0 through 127) of the current tap point and can indicate whether the DLL advances or
decrements as it maintains the DLL lock. Therefore, for evaluation purposes, DTCR can be read for all
DLL modes that support the Tloop value used for the trace length of SDRAM_SYNC_OUT to
SDRAM_SYNC_IN. The DLL mode with the smallest tap point value in the DTCR should be used
because the bigger the tap point value, the more jitter that can be expected for clock signals. Note that
keeping a DLL mode that is locked below tap point decimal 12 is not recommended.
Table 9. DLL Mode Definition
DLL Mode
Bit 2 of Configuration
Register at 0x76
Bit 7 of Configuration
Register at 0x72
Normal tap delay,
No DLL extend
00
Normal tap delay,
DLL extend
01
Max tap delay,
No DLL extend
10
Max tap delay,
DLL extend
11
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