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参数资料
| 型号： | MPC8260ZU150A |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA480 |
| 封装： | 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
| 文件页数： | 46/48页 |
| 文件大小： | 688K |
| 代理商： | MPC8260ZU150A |
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MOTOROLA
MPC826xA (HiP4) Family Hardware Specications
7
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
— Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000)
— Cell counters for performance monitoring
– 16-bit counters count
– HEC error cells
– HEC single bit error and corrected cells
– Idle/unassigned cells ltered
– Idle/unassigned cells transmitted
– Transmitted ATM cells
– Received ATM cells
– Maskable interrupt is sent to the host when a counter expires
— Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt
— May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps
are supported
PCI bridge (MPC8265A and MPC8266A only)
— PCI Specication Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Periphera
l capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the conguration registers (which are automatically loaded from the EPROM
and used to congure the MPC8265A) required by the PCI standard as well as message and
doorbell registers
— Supports the I2O standard
— Hot-Swap friendly (supports the Hot Swap Specication as dened by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specication
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
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