- 您现在的位置：买卖IC网 > PDF目录4051 > MPC8280ZUQLDA (Freescale Semiconductor)IC MPU POWERQUICC II 480-TBGA PDF资料下载
参数资料
| 型号： | MPC8280ZUQLDA |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 19/83页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC II 480-TBGA |
| 标准包装： | 21 |
| 系列： | MPC82xx |
| 处理器类型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 333MHz |
| 电压： | 1.5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 480-LBGA |
| 供应商设备封装： | 408-TBGA（37.5x37.5） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
26
Freescale Semiconductor
Clock Configuration Modes
7
Clock Configuration Modes
This SoC includes the following clocking modes:
Local
PCI host
PCI agent
The clocking mode is set according to the following input pins as shown in the following table:
PCI_MODE
PCI_CFG[0]
PCI_MODCK
Input hold times
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
—
ns
4, 7
Output valid times
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
—
10
ns
5, 7
5. 7
Output hold times
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
1
—
ns
5, 7
JTAG external clock to output high impedance
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
1
10
ns
5, 6
1 All outputs are measured from the midpoint voltage of the falling/rising edge of t
TCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load. Time-of-flight delays
must be added for trace lengths, vias, and connectors in the system.
2 The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t((first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference
(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input
signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3 TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4 Non-JTAG signal input timing with respect to t
TCLK.
5 Non-JTAG signal output timing with respect to t
TCLK.
6 Guaranteed by design.
7 Guaranteed by design and device characterization.
Table 16. JTAG Timings1 (continued)
Parameter
Symbol2
Min
Max
Unit
Notes
相关PDF资料 |
PDF描述 |
|---|---|
| IDT71T75802S133PFG | IC SRAM 18MBIT 133MHZ 100TQFP |
| MPC8280VVQLDA | IC MPU POWERQUICC II 480-TBGA |
| IDT71T75602S150PFG | IC SRAM 18MBIT 150MHZ 100TQFP |
| P1020NSE2HFB | IC MPU 800MHZ 689-TEPBGA2 |
| IDT71T75602S133PFG | IC SRAM 18MBIT 133MHZ 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8280ZUT | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8280ZUUPE | 制造商:Freescale Semiconductor 功能描述: |
| MPC8280ZUUPEA | 功能描述:微处理器 - MPU PQ II HIP 7 REV A RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8280ZUUPEA | 制造商:Freescale Semiconductor 功能描述:IC 32BIT MPU 450MHZ TBGA-480 |
| MPC82E52 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Megawin's product 8051核心增强型单片机，指令周期为1T，内部模块丰富 |
发布紧急采购，3分钟左右您将得到回复。