参数资料
型号: MPC8308-RDB
厂商: Freescale Semiconductor
文件页数: 11/36页
文件大小: 0K
描述: BOARD REF DESIGN MPC8308
产品培训模块: MPC8308 PowerQUICC II Pro Processor
标准包装: 1
系列: PowerQUICC II™ PRO
类型: MPU
适用于相关产品: MPC8308
所含物品: 板,线缆,文档,电源,软件
Board-Level Functions
Table 2. Clock Distribution
Clock Frequency
33.333 MHz
Module
MPC8308 CLKIN
Generated by
33.333 MHz oscillator
Description
The MPC8308 uses CLKIN to generate the
internal system PLL. The CSB clock is
generated by the internal PLL and is fed to the
e300 core PLL for generating the e300 core
clock.
133 MHz
DDR2 SDRAM
MPC8308
The DDR memory controller is configured to use
the 2:1 mode CSB to DDR for the DDR interface
(DDR266). The local bus clock uses 1:1 local to
CSB clock, which is configured by hard reset
configuration or SPMR register.
25 MHz
L2 Switch and GBE PHY
25 MHz oscillator
The 25 MHz oscillator provides the clock for the
L2 switch and the GBE PHY
125 MHz
eTSEC1 clock
125 MHz oscillator
(default)
The eTSEC1 reference clock is provided by
a125MHz oscillator or optionally by the gigabit
or RTL8211B (optional) Ethernet PHY (RTL8211B) on the board.
125 MHz
eTSEC2 clock
125 MHz oscillator
The eTSEC2 reference clock is provided by a
125MHz oscillator.
100 MHz
PCIe/SERDES
PCIe Clock Generator
The PCIe Clock Generator provides differential
clock for PCIe/SERDES module and the PCIe &
mini PCIe slots
50 MHz
IEEE1588 Clock (TMR_CLK)
50 MHz oscillator/ 50
MHz VCXO
50 MHz is used by the IEEE 1588 module. It can
be an ordinary oscillator or VCXO controlled by
SPI DAC.
24 MHz
32.768kHz
32.768kHz
ULPI external USB PHY
MCU MC9S08
RTC DS1339
24 MHz crystal
32.768kHz Crystal
32.768kHz Crystal
Clock for ULPI USB PHY USB3300
Clock for MCU
Clock for RTC
2.4
DDR2 SDRAM Controller
The MPC8308 processor uses DDR2 SDRAM as the system memory. The DDR2 interface uses the SSTL2
driver/receiver and 1.8 V power. A Vref 1.8 V /2 is needed for all SSTL2 receivers in the DDR2 interface.
For details on DDR2 timing design and termination, refer to the Freescale application note entitled
Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582). Signal integrity test
results show this design does not require terminating resistors (series resistor (R S ) and termination resistor
(R T )) for the discrete DDR2 devices used. DDR2 supports on-die termination; the DDR2 chips and
MPC8308 are connected directly. The interface is 1.8 V provided by an on-board voltage regulator. VREF,
which is half the interface voltage, that is, 0.9 V, is provided by a voltage divider of the 1.8 V for voltage
tracking and low cost. One pair of clock pins is provided by the MPC8308, and they are connected and
shared by the two DDR2 devices. Figure 6 shows the DDR2 SDRAM controller connection.
PowerQUICC? MPC8308_RDB User’s Guide, Rev. 3
Micetek International Inc.
11
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