参数资料
型号: MPC8308ZQAGD
厂商: Freescale Semiconductor
文件页数: 72/83页
文件大小: 0K
描述: MPU POWERQUICC II PRO 473MAPBGA
标准包装: 84
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 473-LFBGA
供应商设备封装: 473-MAPBGA(19x19)
包装: 托盘
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 3
74
Freescale Semiconductor
Thermal
21.3
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). This table shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in this table should be considered as reserved.
NOTE
Core VCO frequency = core frequency
VCO divider. The VCO divider,
which is determined by RCWLR[COREPLL], must be set properly so that
the core VCO frequency is in the range of 400–800 MHz.
22 Thermal
This section describes the thermal specifications of the device.
Table 58. e300 Core PLL Configuration
RCWL[COREPLL]
core_clk: csb_clk Ratio1
1 For any core_clk:csb_clk ratios, the core_clk must not exceed its maximum operating frequency of 400 MHz.
VCO Divider (VCOD)2
2 Core VCO frequency = core frequency
VCO divider. Note that VCO divider has to be set properly so that the
core VCO frequency is in the range of 400–800 MHz.
0–1
2–5
6
nn
0000
0
PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core directly)
11
nnnn
nn/a
n/a
00
0001
01:1
2
01
0001
01:1
4
10
0001
01:1
8
00
0001
1
1.5:1
2
01
0001
1
1.5:1
4
10
0001
1
1.5:1
8
00
0010
02:1
2
01
0010
02:1
4
10
0010
02:1
8
00
0010
1
2.5:1
2
01
0010
1
2.5:1
4
10
0010
1
2.5:1
8
00
0011
03:1
2
01
0011
03:1
4
10
0011
03:1
8
Note:
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