参数资料
型号: MPC8313ZQADDB
厂商: Freescale Semiconductor
文件页数: 23/99页
文件大小: 0K
描述: MPU POWERQUICC II PRO 516-PBGA
标准包装: 40
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 267MHz
电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
封装/外壳: 516-BBGA 裸露焊盘
供应商设备封装: 516-PBGAPGE(27x27)
包装: 托盘
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
3
1.2
Serial Interfaces
The following interfaces are supported in the MPC8313E: dual UART, dual I2C, and an SPI interface.
1.3
Security Engine
The security engine is optimized to handle all the algorithms associated with IPSec, IEEE Std 802.11i,
and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution
units (EUs). The execution units are as follows:
Data encryption standard execution unit (DEU), supporting DES and 3DES
Advanced encryption standard unit (AESU), supporting AES
Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-224, SHA-256, and
HMAC with any algorithm
One crypto-channel supporting multi-command descriptor chains
1.4
DDR Memory Controller
The MPC8313E DDR1/DDR2 memory controller includes the following features:
Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM
Support for up to 333 MHz
Support for two physical banks (chip selects), each bank independently addressable
64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16/x32 data ports (no
direct x4 support)
Support for one 16-bit device or two 8-bit devices on a 16-bit bus, or one 32-bit device or two
16-bit devices on a 32-bit bus
Support for up to 16 simultaneous open pages
Supports auto refresh
On-the-fly power management using CKE
1.8-/2.5-V SSTL2 compatible I/O
1.5
PCI Controller
The MPC8313E PCI controller includes the following features:
PCI specification revision 2.3 compatible
Single 32-bit data PCI interface operates at up to 66 MHz
PCI 3.3-V compatible (not 5-V compatible)
Support for host and agent modes
On-chip arbitration, supporting three external masters on PCI
Selectable hardware-enforced coherency
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