参数资料
型号: MPC8313ZQAFF
厂商: Freescale Semiconductor
文件页数: 2/99页
文件大小: 0K
描述: IC MPU POWERQUICC II PRO 516PBGA
标准包装: 40
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
电压: 0.95 V ~ 1.05 V
安装类型: 表面贴装
封装/外壳: 516-BBGA 裸露焊盘
供应商设备封装: 516-PBGAPGE(27x27)
包装: 托盘
配用: MPC8313E-RDB-ND - BOARD PROCESSOR
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
10
Freescale Semiconductor
2.2
Power Sequencing
The MPC8313E does not require the core supply voltage (VDD and VDDC) and I/O supply voltages
(GVDD, LVDD, and NVDD) to be applied in any particular order. Note that during power ramp-up, before
the power supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a
period of time that all input and output pins are actively driven and cause contention and excessive current.
In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core
voltage (VDD and VDDC) before the I/O voltage (GVDD, LVDD, and NVDD) and assert PORESET before
the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the
power supplies (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before
negating PORESET.
Note that there is no specific power down sequence requirement for the MPC8313E. I/O voltage supplies
(GVDD, LVDD, and NVDD) do not have any ordering requirements with respect to one another.
Figure 3. Power-Up Sequencing Example
DDR2 signal
18
GVDD = 1.8 V
DUART, system control, I2C, JTAG, SPI
42
NVDD = 3.3 V
GPIO signals
42
NVDD = 3.3 V
eTSEC signals
42
LVDDA, LVDDB = 2.5/3.3 V
USB signals
42
LVDDB = 2.5/3.3 V
Table 3. Output Drive Capability (continued)
Driver Type
Output Impedance (
)
Supply Voltage
t
90%
V
Core Voltage (VDD, VDDC)
I/O Voltage (GVDD, GVDD, and NVDD)
0
0.7 V
PORESET
tSYS_CLK_IN/tPCI_SYNC_IN >= 32 clocks
相关PDF资料
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