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| 型号： | MPC8343CZQAGD |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 71/80页 |
| 文件大小： | 0K |
| 描述： | IC MPU PWRQUICC II PRO 620-PBGA |
| 标准包装： | 36 |
| 系列： | MPC83xx |
| 处理器类型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 400MHz |
| 电压： | 1.2V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 620-BBGA 裸露焊盘 |
| 供应商设备封装： | 620-PBGA（29x29） |
| 包装： | 托盘 |
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MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
73
System Design Information
RθJC = junction-to-case thermal resistance (°C/W)
PD = power dissipation (W)
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8343EA.
21.1
System Clocking
The MPC8343EA includes two PLLs:
1. The platform PLL generates the platform clock from the externally supplied CLKIN input. The
frequency ratio between the platform and CLKIN is selected using the platform PLL ratio
configuration bits as described in Section 19.1, “System PLL Configuration.”
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in Section 19.2, “Core PLL Configuration.”
21.2
PLL Power Supply Filtering
Each PLL gets power through independent power supply pins (AVDD1, AVDD2, respectively). The AVDD
level should always equal to VDD, and preferably these voltages are derived directly from VDD through a
low frequency filter scheme.
There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to
provide four independent filter circuits as illustrated in Figure 38, one to each of the four AVDD pins.
Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other.
The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built
with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the
recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic
(Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value
capacitor.
To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the
specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
Figure 38 shows the PLL power supply filter circuit.
Figure 38. PLL Power Supply Filter Circuit
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
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相关代理商/技术参数 |
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| MPC8343CZQAGDB | 功能描述:微处理器 - MPU 8347 PBGA W/O ENC W/ PB RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8343EA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications |
| MPC8343ECVRADDB | 功能描述:微处理器 - MPU 8347 PBGA NO-PB W/ ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8343ECVRAGD | 功能描述:IC MPU PWRQUICC II PRO 620-PBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:MPC83xx 标准包装:1 系列:MPC85xx 处理器类型:32-位 MPC85xx PowerQUICC III 特点:- 速度:1.2GHz 电压:1.1V 安装类型:表面贴装 封装/外壳:783-BBGA，FCBGA 供应商设备封装:783-FCPBGA（29x29） 包装:托盘 |
| MPC8343ECVRAGDB | 功能描述:微处理器 - MPU 8347 PBGA NO-PB W/ ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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