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| 型号： | MPC8347ECZQAJF |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA620 |
| 封装： | 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620 |
| 文件页数： | 22/102页 |
| 文件大小： | 1094K |
| 代理商： | MPC8347ECZQAJF |
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MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
26
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Figure 10 shows the MII transmit AC timing diagram.
Figure 10. MII Transmit AC Timing Diagram
8.2.2.2
MII Receive AC Timing Specifications
Table 24 provides the MII receive AC timing specifications.
Figure 11 provides the AC test load for TSEC.
Figure 11. TSEC AC Test Load
Table 24. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
RX_CLK clock period 10 Mbps
tMRX
—400
—
ns
RX_CLK clock period 100 Mbps
tMRX
—40
—
ns
RX_CLK duty cycle
tMRXH/tMRX
35
—
65
%
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
tMRDVKH
10.0
—
ns
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
ns
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0—
4.0ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0—
4.0ns
Note:
1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing
(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to
the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. In general, the clock
reference symbol is based on three letters representing the clock of a particular functionl. For example, the subscript of tMRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
R (rise) or F (fall).
TX_CLK
TXD[3:0]
tMTKHDX
tMTX
tMTXH
tMTXR
tMTXF
TX_EN
TX_ER
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8347ECZQAJFB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications |
| MPC8347ECZQALDB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications |
| MPC8347ECZQALFB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications |
| MPC8347ECZUADDB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications |
| MPC8347ECZUADFB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications |
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