参数资料
型号: MPC8347EZQAGDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封装: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件页数: 21/120页
文件大小: 1349K
代理商: MPC8347EZQAGDA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
117
Document Revision History
22 Document Revision History
Table 66 provides a revision history of this document.
23 Ordering Information
This section presents ordering information for the device discussed in this document, and it shows an
example of how the parts are marked.
23.1
Part Numbers Fully Addressed by this Document
Table 67 shows an analysis of the Freescale part numbering nomenclature for the MPC8347EA. The
individual part numbers correspond to a maximum processor core frequency. For available frequencies,
contact your local Freescale sales office. Also the part numbering scheme includes an application modifier
to specify special application conditions. Each part number also contains a revision code that refers to the
die mask revision number.
Table 69. Document Revision History
Revision
Date
Substantive Change(s)
2
8/2006
Changed all references to revision 2.0 silicon to revision 3.0 silicon.
Changed VIH minimum value in Table 36, “JTAG Interface DC Electrical Characteristics,” to
OVDD –0.3.
In Table 60, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
In Table 40, “PCI DC Electrical Characteristics,” changed higl-level input voltage values to min = 2
and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
In Table 44, “PCI DC Electrical Characteristics,” changed higl-level input voltage values to min = 2
and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
Updated DDR2 I/O power values in Table 9, “MPC8347EA Typical I/O Power Dissipation.”
1
4/2006
Removed Table 20, “Timing Parameters for DDR2-400.”
Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Changed Min and Max values for VIH and VIL in Table 40,“PCI DC Electrical Characteristics.”
In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” modified rows for MDICO and MDIC1 signals and added note “It is recommended that
MDICO be tied to GRD using an 18
Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.”
In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
Listing,” in row AVDD3 changed power supply from “AVDD3” to “—.”
0
3/2006
Initial Release
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