参数资料
型号: MPC8349ZUAJDA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 533 MHz, MICROPROCESSOR, PBGA672
封装: 35 X 35 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-672
文件页数: 36/112页
文件大小: 1295K
代理商: MPC8349ZUAJDA
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
3
Overview
— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep-mode support for SDRAM self refresh
— Auto refresh
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual controllers designed to comply with IEEE Std. 802.3, 802.3u, 820.3x, 802.3z, 802.3ac
— Ethernet physical interfaces:
– 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
Dual PCI interfaces
— Designed to comply with PCI specification revision 2.3
— Data bus width options:
– Dual 32-bit data PCI interfaces operating at up to 66 MHz
– Single 64-bit data PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— PCI host bridge capabilities on both interfaces
— PCI agent mode on PCI1 interface
— PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration supporting five masters on PCI1, three masters on PCI2
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
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