参数资料
型号: MPC8358CVRAGDGA
厂商: Freescale Semiconductor
文件页数: 10/95页
文件大小: 0K
描述: MPU POWERQUICC II PRO 668-PBGA
标准包装: 36
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
电压: 1.2V
安装类型: 表面贴装
封装/外壳: 668-BBGA 裸露焊盘
供应商设备封装: 668-PBGA-PGE(29x29)
包装: 托盘
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
18
Freescale Semiconductor
DDR and DDR2 SDRAM
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface
of the MPC8358E.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 13 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GVDD(typ) = 1.8 V.
UART/async HDLC
3.68 (max internal ref
clock)
115 (Kbps)
20
BISYNC
2 (max)
2
20
USB
48 (ref clock)
12
96
Notes:
1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.
2. ‘F’ is the actual interface operating frequency.
3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).
4. TDM in high-speed mode for serial data interface.
Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
1.71
1.89
V
1
I/O reference voltage
MVREF
0.49
× GVDD
0.51
× GVDD
V2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.125
GVDD + 0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.125
V
Output leakage current
IOZ
—±10
μA4
Output high current (VOUT = 1.420 V)
IOH
–13.4
mA
Output low current (VOUT = 0.280 V)
IOL
13.4
mA
MVREF input leakage current
IVREF
—±10
μA—
Table 12. QUICC Engine Block Operating Frequency Limitations (continued)
Interface
Interface Operating
Frequency (MHz)
Max Interface Bit
Rate (Mbps)
Min QUICC Engine
Operating
Frequency1 (MHz)
Notes
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