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| 型号： | MPC8360ZUAGDHA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA740 |
| 封装： | 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-740 |
| 文件页数： | 19/102页 |
| 文件大小： | 606K |
| 代理商： | MPC8360ZUAGDHA |
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MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
23
DDR and DDR2 SDRAM AC Electrical Characteristics
This figure shows the DDR SDRAM output timing for address skew with respect to any MCK.
Figure 7. Timing Diagram for tAOSKEW Measurement
MDQS epilogue end
tDDKHME
–0.6
0.9
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in applied cycle increments through the clock control register.
For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the
address/command valid with the rising edge of MCK.
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks
by applied cycle.
5. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this is typically set to the
same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. Refer MPC8360E PowerQUICC II Pro Integrated Communications
Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits.
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that tDDKHMP follows the symbol
conventions described in note 1.
8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
9. In rev. 2.0 silicon, tDDKHMH maximum meets the specification of 0.6 ns. In rev. 2.0 silicon, due to errata, tDDKHMH minimum
is –0.9 ns. Refer to Errata DDR18 in Chip Errata for the MPC8360E, Rev. 1.
Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
Synchronous Mode (continued)
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.
Parameter8
Symbol1
Min
Max
Unit
Notes
ADDR/CMD
MCK[n]
tMCK
CMD
NOOP
tAOSKEW(min)
ADDR/CMD
CMD
NOOP
tAOSKEW(max)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8360ZUAGFGA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360ZUAGFHA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications |
| MPC8360ZUAHFH | 功能描述:微处理器 - MPU 8360 TBGA NON-ENCRP RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8360ZUAJDG | 功能描述:微处理器 - MPU 8360 TBGA NON-ENCRP RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
| MPC8360ZUAJDGA | 功能描述:微处理器 - MPU 8360 TBGA NON-ENCRP RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324 |
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