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参数资料
型号： MPC8377EVRAGD
厂商： Freescale Semiconductor
文件页数： 78/127页
文件大小： 0K
描述： MPU PWRQUICC II 400MHZ 689TEPBGA
产品培训模块： MPC837x PowerQUICC II Pro Processors
视频文件： Introduction to the MPC837x Family
标准包装： 27
系列： MPC83xx
处理器类型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
电压： 1V
安装类型： 表面贴装
封装/外壳： 689-BBGA 裸露焊盘
供应商设备封装： 689-TEPBGA II（31x31）
包装： 托盘
配用： MPC8377E-RDBA-ND - BOARD REF DES MPC8377 REV 2.1
MPC8377E-MDS-PB-ND - BOARD MODULAR DEV SYSTEM
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
54
Freescale Semiconductor
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 32. AC Test Load for the JTAG Interface
This figure provides the JTAG clock input timing diagram.
Figure 33. JTAG Clock Input Timing Diagram
This figure provides the TRST timing diagram.
Figure 34. TRST Timing Diagram
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
19
9
ns
5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50
Ω load (see
Figure 17). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect
to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
Table 45. JTAG AC Timing Specifications (Independent of CLKIN) 1 (continued)
Parameter
Symbol2
Min
Max
Unit
Note
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
JTAG
tJTKHKL
tJTGR
External Clock
VM
tJTG
tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM
tTRST
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相关代理商/技术参数
参数描述
MPC8377EVRAGDA 功能描述:微处理器 - MPU 8377 PBGA ST PbFr W/ENC RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
MPC8377EVRAGFA 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
MPC8377EVRAGGA 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
MPC8377EVRAJDA 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications
MPC8377EVRAJF 功能描述:微处理器 - MPU PBGA W/ ENCR RoHS:否 制造商:Atmel 处理器系列:SAMA5D31 核心:ARM Cortex A5 数据总线宽度:32 bit 最大时钟频率:536 MHz 程序存储器大小:32 KB 数据 RAM 大小:128 KB 接口类型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作电源电压:1.8 V to 3.3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-324
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