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| 型号： | MPC8377EWLANB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 48/127页 |
| 文件大小： | 0K |
| 描述： | ACCESS POINT/ROUTER MPC8377 |
| 标准包装： | 1 |
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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
27
This figure shows the MII receive AC timing diagram.
Figure 9. MII Receive AC Timing Diagram
8.2.2
RGMII and RTBI AC Timing Specifications
This table presents the RGMII and RTBI AC timing specifications.
Table 28. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
Note
Data to clock output skew (at transmitter)
tSKRGT
–600
0
600
ps
—
Data to clock input skew (at receiver)
tSKRGT
1.0
—
2.8
ns
Clock period
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T
tRGTH/tRGT
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
0.75
ns
—
Fall time (20%–80%)
tRGTF
—
0.75
ns
—
EC_GTX_CLK125 reference clock period
tG12
—8.0
—
ns
EC_GTX_CLK125 reference clock duty cycle
measured at 0.5
× LVDD1
tG125H/tG125
47
—
53
%
—
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being
represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between
5. This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention.
RX_CLK
RXD[3:0]
tMRDXKL
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
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| MPC8377EZQAFDA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8377EZQAFFA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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