参数资料
型号: MPC8378ECVRAJFA
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 333 MHz, MICROPROCESSOR, PBGA689
封装: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数: 11/125页
文件大小: 894K
代理商: MPC8378ECVRAJFA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
108
22.1
System PLL Configuration
The system PLL is controlled by the RCWLR[SPMF] parameter. The system PLL VCO frequency depends on
RCWLR[DDRCM] and RCWLR[LBCM]. Table 71 shows the multiplication factor encodings for the system PLL.
NOTE
If RCWLR[DDRCM] and RCWLR[LBCM] are both cleared, the system PLL VCO
frequency = (CSB frequency)
(System PLL VCO Divider).
If either RCWLR[DDRCM] or RCWLR[LBCM] are set, the system PLL VCO frequency
= 2
(CSB frequency) (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO frequency is in the
range of 400–800 MHz.
Local bus controller frequency (lbc_clk)—
400
PCI input frequency (CLKIN or PCI_CLK)
25
66
eTSEC frequency
133
400
Security encryption controller frequency
200
USB controller frequency
200
eSDHC controller frequency
200
PCI Express controller frequency
400
Notes:
1. The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting csb_clk,
MCK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The
value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core, USB
modules, SATA, and eSDHC will not exceed their respective value listed in this table.
2. The DDR data rate is 2
the DDR memory bus frequency.
3. The local bus frequency is , , or 1/8 of the lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the csb_clk frequency (depending on RCWLR[LBCM]).
Table 71. System PLL Multiplication Factors
RCWLR[SPMF]
System PLL Multiplication Factor
0000
Reserved
0001
Reserved
0010
2
0011
3
0100
4
0101
5
0110
6
0111–1111
7 to 15
Table 70. Operating Frequencies for TePBGA II (continued)
Parameter1
Minimum Operating
Frequency (MHz)
Maximum Operating
Frequency (MHz)
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