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参数资料
型号： MPC8378ECVRALDA
厂商： FREESCALE SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封装： 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件页数： 28/125页
文件大小： 894K
代理商： MPC8378ECVRALDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
123
26
Document Revision History
The following table provides a revision history for this document.
Table 83. Document Revision History
Revision
Date
Substantive Change(s)
5
07/2011 In Table 2, “Absolute Maximum Ratings1,” removed footnote 5 from LBIN to OVIN. Also, corrected
footnote 5.
In Table 3, “Recommended Operating Conditions,” added footnote 2 to AVDD.
In Figure 2, “Overshoot/Undershoot Voltage for GVDD/LVDD/OVDD/LBVDD,” added LBVDD.
In Table 13, “DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V,” updated IOZ min/max
to –50/50.
In Figure 15, “RGMII and RTBI AC Timing and Multiplexing Diagrams,” added distinction between
tSKRGT_RX and tSKRGT_TX signals.
In Table 38, “MII Management AC Timing Specifications,” updated MDC frequency—removed Min and
Max values, added Typical value. Also, updated footnote 2and removed footnote 3.
In Table 53, “PCI DC Electrical Characteristics,” updated VIH min value to 2.0.
In Table 68, “TePBGA II Pinout Listing,” added Note to LGPL4/LFRB_B/LGTA_B/LUPWAIT/LPBSE (to
be consistent with AN3665, “MPC837xE Design Checklist.”
In Table 70, “Operating Frequencies for TePBGA II,” added Minimum Operating Frequency for eTSEC,
and corrected DDR2 Minimum and Maximum Operating Frequency values.
4
11/2010 In Table 25, “RGMII and RTBI DC Electrical Characteristics,” updated VIH min value to 1.7.
In Table 45, “Local Bus General Timing Parameters—PLL Bypass Mode,” added row for tLBKHLR.
In Section 10.2, “Local Bus AC Electrical Specifications,” and in Section 22, “Clocking,” updated LCCR
to LCRR.
In Table 68, “TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and
TEST_SEL1 pins—no change in functionality.
3
03/2010 Added Section 4.3, “eTSEC Gigabit Reference Clock Timing.”
In Table 39, “USB DC Electrical Characteristics,” and Table 40, “USB General Timing Parameters (ULPI
Mode Only),” added table footnotes .
In Table 44, “Local Bus General Timing Parameters—PLL Enable Mode,” and Table 45, “Local Bus
General Timing Parameters—PLL Bypass Mode,” corrected footnotes for tLBOTOT1, tLBOTOT2, tLBOTOT3.
In Figure 26, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode),” and
Figure 28, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode),” shifted
“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.
In Figure 66, “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added heat
spreader.
In Section 24.6, “Pull-Up Resistor Requirements,” removed “Ethernet Management MDIO pin” from list
of open drain type pins.
In Table 68, “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and
AVDD_P pins.
in Table 68, “TePBGA II Pinout Listing,” added Note 17 to eTSEC pins.
In Table 73, “CSB Frequency Options for Host Mode,” and Table 74, “CSB Frequency Options for Agent
Mode,” updated csb_clk frequencies available.
In Table 80, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”
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